2022-12-28 08:44:20 +08:00
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-02-22 airm2m first version
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <air32f10x_conf.h>
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#include "drv_common.h"
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#include "drv_gpio.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define AIR32_FLASH_START_ADRESS ((uint32_t)0x08000000)
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#define FLASH_PAGE_SIZE (64)
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#define AIR32_FLASH_SIZE (128 * 1024)
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#define AIR32_FLASH_END_ADDRESS ((uint32_t)(AIR32_FLASH_START_ADRESS + AIR32_FLASH_SIZE))
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2023-05-12 09:24:05 +08:00
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/* Internal SRAM memory size[Kbytes] , Default: 96*/
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#define AIR32_SRAM_SIZE 96
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2022-12-28 08:44:20 +08:00
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#define AIR32_SRAM_END (0x20000000 + AIR32_SRAM_SIZE * 1024)
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#if defined(__ARMCC_VERSION)
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="CSTACK"
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#define HEAP_BEGIN (__segment_end("CSTACK"))
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#else
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extern int __bss_end;
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#define HEAP_BEGIN ((void *)&__bss_end)
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#endif
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#define HEAP_END AIR32_SRAM_END
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void SystemClock_Config(void);
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#ifdef BSP_USING_UART
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void air32_usart_clock_and_io_init(USART_TypeDef *usartx);
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#endif
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#ifdef BSP_USING_SPI
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void air32_spi_clock_and_io_init(SPI_TypeDef* spix);
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rt_uint32_t air32_spi_clock_get(SPI_TypeDef* spix);
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#endif
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#ifdef BSP_USING_TIM
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void air32_tim_clock_init(TIM_TypeDef *timx);
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rt_uint32_t air32_tim_clock_get(TIM_TypeDef *timx);
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#endif
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#ifdef BSP_USING_TIM
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struct rt_hwtimer_info* air32_hwtimer_info_config_get(TIM_TypeDef *timx);
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#endif
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#ifdef BSP_USING_PWM
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void air32_pwm_io_init(TIM_TypeDef *timx, rt_uint8_t channel);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __BOARD_H__ */
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