95 lines
3.5 KiB
C
95 lines
3.5 KiB
C
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/*
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* @brief FPU init code
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#if defined(CORE_M4)
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#include "stdint.h"
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/*****************************************************************************
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* Private types/enumerations/variables
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****************************************************************************/
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#define LPC_CPACR 0xE000ED88
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#define SCB_MVFR0 0xE000EF40
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#define SCB_MVFR0_RESET 0x10110021
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#define SCB_MVFR1 0xE000EF44
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#define SCB_MVFR1_RESET 0x11000011
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/*****************************************************************************
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* Public types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Private functions
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****************************************************************************/
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/*****************************************************************************
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* Public functions
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****************************************************************************/
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/* Early initialization of the FPU */
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void fpuInit(void)
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{
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// from arm trm manual:
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// ; CPACR is located at address 0xE000ED88
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// LDR.W R0, =0xE000ED88
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// ; Read CPACR
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// LDR R1, [R0]
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// ; Set bits 20-23 to enable CP10 and CP11 coprocessors
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// ORR R1, R1, #(0xF << 20)
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// ; Write back the modified value to the CPACR
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// STR R1, [R0]
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volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
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volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
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volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
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volatile uint32_t Cpacr;
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volatile uint32_t Mvfr0;
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volatile uint32_t Mvfr1;
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char vfpPresent = 0;
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Mvfr0 = *regMvfr0;
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Mvfr1 = *regMvfr1;
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vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
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if (vfpPresent) {
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Cpacr = *regCpacr;
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Cpacr |= (0xF << 20);
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*regCpacr = Cpacr; // enable CP10 and CP11 for full access
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}
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}
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#endif /* defined(CORE_M4 */
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