183 lines
8.1 KiB
C
183 lines
8.1 KiB
C
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/*
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* @brief ADC Registers and control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __ADC_001_H_
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#define __ADC_001_H_
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#include "sys_config.h"
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup IP_ADC_001 IP: 10 or 12-bit ADC register block and driver
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* @ingroup IP_Drivers
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* @{
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*/
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/**
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* @brief 10 or 12-bit ADC register block structure
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*/
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typedef struct { /*!< ADCn Structure */
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__IO uint32_t CR; /*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
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__I uint32_t GDR; /*!< A/D Global Data Register. Contains the result of the most recent A/D conversion. */
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__I uint32_t RESERVED0;
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__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
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__I uint32_t DR[8]; /*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
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__I uint32_t STAT; /*!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
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#if !defined(CHIP_LPC18XX) && !defined(CHIP_LPC43XX)
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__IO uint32_t ADTRM;
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#endif
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} IP_ADC_001_Type;
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/**
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* @brief ADC register support bitfields and mask
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*/
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#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /*!< Mask for getting the ADC data read value */
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#define ADC_DR_DONE(n) (((n) >> 31)) /*!< Mask for reading the ADC done status */
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#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /*!< Mask for reading the ADC overrun status */
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#define ADC_CR_CH_SEL(n) ((1UL << (n))) /*!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
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#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
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#define ADC_CR_BURST ((1UL << 16)) /*!< Repeated conversions A/D enable bit */
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#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /*!< Number of ADC accuracy bits */
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#define ADC_CR_PDN ((1UL << 21)) /*!< ADC convert in power down mode */
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#define ADC_CR_START_MASK ((7UL << 24)) /*!< ADC start mask bits */
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#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /*!< Select Start Mode */
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#define ADC_CR_START_NOW ((1UL << 24)) /*!< Start conversion now */
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#define ADC_CR_START_CTOUT15 ((2UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
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#define ADC_CR_START_CTOUT8 ((3UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
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#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
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#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
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#define ADC_CR_START_MCOA2 ((6UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
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#define ADC_CR_EDGE ((1UL << 27)) /*!< Start conversion on a falling edge on the selected CAP/MAT signal */
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/**
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* @brief ADC status register used for IP drivers
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*/
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typedef enum {
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ADC_DR_DONE_STAT, /*!< ADC data register staus */
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ADC_DR_OVERRUN_STAT,/*!< ADC data overrun staus */
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ADC_DR_ADINT_STAT /*!< ADC interrupt status */
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} IP_ADC_Status;
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/**
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* @brief Initialize for ADC
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* @param pADC : The base of ADC peripheral on the chip
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* @param adcRate : Sample rate of A/D converter
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* @param adcPerClock : The APB clock
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* @param bitsAccuracy : The accuracy of LSB value, should be ADC_10BITS -> ADC_3BITS
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* @return Nothing
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* Disable all ADC interrupts, set bit PDN, set ADC clock frequency
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* This is not the sample rate, but the clock for the ADC machine, and is usually set to
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* maximum. Applications may choose a lower frequency if they have high-impedance sources.
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* This is because a lower clock frequency produces a longer sampling time.
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*/
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void IP_ADC_Init(IP_ADC_001_Type *pADC, uint32_t adcRate, uint32_t adcPerClock, uint8_t bitsAccuracy);
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/**
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* @brief Shutdown ADC
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* @param pADC : The base of ADC peripheral on the chip
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* @return Nothing
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* Reset the ADC control and INTEN Register to reset values (disabled)
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*/
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void IP_ADC_DeInit(IP_ADC_001_Type *pADC);
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/**
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* @brief Set burst mode for ADC
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* @param pADC : The base of ADC peripheral on the chip
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* @param NewState : ENABLE for burst mode, or DISABLE for normal mode
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* @return Nothing
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*/
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void IP_ADC_SetBurstMode(IP_ADC_001_Type *pADC, FunctionalState NewState);
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/**
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* @brief Get the ADC value
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* @param pADC : The base of ADC peripheral on the chip
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* @param channel : Channel to be read value, should be 0..7
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* @param data : Data buffer to store the A/D value
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* @return Status : SUCCESS or ERROR
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*/
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Status IP_ADC_Get_Val(IP_ADC_001_Type *pADC, uint8_t channel, uint16_t *data);
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/**
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* @brief Get ADC Channel status from ADC data register
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* @param pADC : The base of ADC peripheral on the chip
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* @param channel : Channel number, should be 0..7
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* @param StatusType : Register to read, ADC_DR_DONE_STAT, ADC_DR_OVERRUN_STAT, or ADC_DR_ADINT_STAT
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* @return Channel status, SET or RESET
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*/
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FlagStatus IP_ADC_GetStatus(IP_ADC_001_Type *pADC, uint8_t channel, uint32_t StatusType);
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/**
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* @brief Set the edge start condition
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* @param pADC : The base of ADC peripheral on the chip
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* @param edge_mode : 0 = rising, != = falling
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* @return Nothing
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*/
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void IP_ADC_EdgeStartConfig(IP_ADC_001_Type *pADC, uint8_t edge_mode);
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/**
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* @brief Enable/Disable ADC channel number
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* @param pADC : The base of ADC peripheral on the chip
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* @param channel : Channel number
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* @param NewState : New state, ENABLE or DISABLE
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* @return Nothing
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*/
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void IP_ADC_SetChannelNumber(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState);
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/**
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* @brief Set start mode for ADC
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* @param pADC : The base of ADC peripheral on the chip
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* @param start_mode : Start mode choose one of modes in 'ADC_START_*' enumeration type definitions
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* @return Nothing
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*/
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void IP_ADC_SetStartMode(IP_ADC_001_Type *pADC, uint8_t start_mode);
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/**
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* @brief Enable/Disable interrupt for ADC channel
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* @param pADC : The base of ADC peripheral on the chip
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* @param channel : Channel assert the interrupt
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* @param NewState : New state, ENABLE or DISABLE
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* @return Nothing
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*/
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void IP_ADC_Int_Enable(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ADC_001_H_ */
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