2022-01-07 13:49:06 +08:00
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-10-26 bigmagic first version
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*/
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#include <rthw.h>
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#include "drv_wdt.h"
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2022-03-29 11:08:25 +08:00
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#include "drv_gpio.h"
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#include "mbox.h"
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2022-01-07 13:49:06 +08:00
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#include "raspi4.h"
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#ifdef BSP_USING_WDT
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#define SECS_TO_WDOG_TICKS(x) ((x) << 16)
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#define WDOG_TICKS_TO_SECS(x) ((x) >> 16)
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static struct raspi_wdt_driver bcm_wdt;
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void raspi_watchdog_init(rt_uint32_t time_init)
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{
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bcm_wdt.timeout = time_init;
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}
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void raspi_watchdog_start()
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{
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volatile rt_uint32_t cur;
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PM_WDOG = PM_PASSWORD | (SECS_TO_WDOG_TICKS(bcm_wdt.timeout) & PM_WDOG_TIME_SET);
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cur = (PM_RSTC);
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PM_RSTC = PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
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}
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void raspi_watchdog_stop()
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{
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PM_RSTC = PM_PASSWORD | PM_RSTC_RESET;
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}
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void raspi_watchdog_clr()
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{
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bcm_wdt.timeout = 0;
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}
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void raspi_watchdog_set_timeout(rt_uint32_t timeout_us)
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{
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bcm_wdt.timeout = timeout_us;
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}
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rt_uint64_t raspi_watchdog_get_timeout()
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{
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return bcm_wdt.timeout;
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}
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rt_uint64_t raspi_watchdog_get_timeleft()
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{
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rt_uint32_t ret = (PM_WDOG);
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return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET);
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}
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static rt_err_t raspi_wdg_init(rt_watchdog_t *wdt)
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{
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/* init for 10S */
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raspi_watchdog_init(1000000);
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raspi_watchdog_start();
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raspi_watchdog_stop();
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return RT_EOK;
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}
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static rt_err_t raspi_wdg_control(rt_watchdog_t *wdt, int cmd, void *arg)
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{
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rt_uint64_t timeout_us = 0;
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switch (cmd)
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{
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case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
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timeout_us = *((rt_uint32_t *)arg) * 1000000;
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if (timeout_us >= 0xFFFFFFFF)
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{
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timeout_us = 0xFFFFFFFF;
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}
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raspi_watchdog_set_timeout((rt_uint32_t)timeout_us);
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break;
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case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
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timeout_us = raspi_watchdog_get_timeout();
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*((rt_uint32_t *)arg) = timeout_us / 1000000;
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break;
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case RT_DEVICE_CTRL_WDT_GET_TIMELEFT:
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timeout_us = raspi_watchdog_get_timeleft();
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*((rt_uint32_t *)arg) = timeout_us / 1000000;
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break;
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case RT_DEVICE_CTRL_WDT_KEEPALIVE:
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raspi_watchdog_clr();
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break;
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case RT_DEVICE_CTRL_WDT_START:
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raspi_watchdog_start();
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break;
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case RT_DEVICE_CTRL_WDT_STOP:
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raspi_watchdog_stop();
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break;
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default:
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2023-03-17 01:12:51 +08:00
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return -RT_EIO;
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2022-01-07 13:49:06 +08:00
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}
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return RT_EOK;
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}
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static const struct rt_watchdog_ops raspi_wdg_pos =
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{
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raspi_wdg_init,
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raspi_wdg_control,
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};
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static rt_watchdog_t raspi_wdg;
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int rt_hw_wdt_init(void)
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{
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raspi_wdg.ops = &raspi_wdg_pos;
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rt_hw_watchdog_register(&raspi_wdg, "wdg", 0, RT_NULL);
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return RT_EOK;
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}
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INIT_DEVICE_EXPORT(rt_hw_wdt_init);
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2022-03-29 11:08:25 +08:00
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void poweroff(void)
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{
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unsigned long r;
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rt_kprintf("poweroff...\n");
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/* power off devices one by one */
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for (r = 0; r < 16; ++r)
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{
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bcm271x_mbox_poweroff_devices(r);
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}
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/* power off gpio pins (but not VCC pins) */
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GPIO_REG_GPFSEL0(GPIO_BASE) = 0;
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GPIO_REG_GPFSEL1(GPIO_BASE) = 0;
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GPIO_REG_GPFSEL2(GPIO_BASE) = 0;
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GPIO_REG_GPFSEL3(GPIO_BASE) = 0;
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GPIO_REG_GPFSEL4(GPIO_BASE) = 0;
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GPIO_REG_GPFSEL5(GPIO_BASE) = 0;
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GPIO_REG_GPPUD(GPIO_BASE) = 0;
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rt_thread_mdelay(150);
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GPIO_REG_GPPUDCLK0(GPIO_BASE) = 0xffffffff;
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GPIO_REG_GPPUDCLK1(GPIO_BASE) = 0xffffffff;
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rt_thread_mdelay(150);
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/* flush GPIO setup */
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GPIO_REG_GPPUDCLK0(GPIO_BASE) = 0;
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GPIO_REG_GPPUDCLK1(GPIO_BASE) = 0;
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/* power off the SoC (GPU + CPU), partition 63 used to indicate halt */
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r = PM_RSTS;
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r &= ~0xfffffaaa;
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r |= 0x555;
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PM_RSTS |= PM_PASSWORD | r;
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PM_WDOG |= PM_PASSWORD | 0x0A;
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PM_RSTC |= PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET;
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while (1) {};
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}
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MSH_CMD_EXPORT(poweroff, poweroff...);
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2022-01-07 13:49:06 +08:00
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void reboot(void)
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{
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unsigned int r;
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rt_kprintf("reboot system...\n");
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rt_thread_mdelay(100);
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r = PM_RSTS;
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/* trigger a restart by instructing the GPU to boot from partition 0 */
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r &= ~0xfffffaaa;
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PM_RSTS |= (PM_PASSWORD | r); /* boot from partition 0 */
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PM_WDOG |= (PM_PASSWORD | 0x0A);
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PM_RSTC |= (PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET);
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while (1) {};
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}
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MSH_CMD_EXPORT(reboot, reboot system...);
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#endif /*BSP_USING_WDT */
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