2017-11-17 20:07:04 +08:00
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mainmenu "RT-Thread Configuration"
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2019-01-16 23:23:38 +08:00
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config BSP_DIR
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2017-11-17 20:07:04 +08:00
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string
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option env="BSP_ROOT"
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default "."
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2019-01-16 23:23:38 +08:00
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config RTT_DIR
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2017-11-17 20:07:04 +08:00
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string
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option env="RTT_ROOT"
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default "../.."
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2019-01-16 23:23:38 +08:00
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config PKGS_DIR
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2017-11-17 20:07:04 +08:00
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string
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option env="PKGS_ROOT"
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default "packages"
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2017-11-30 20:12:53 +08:00
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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2017-11-17 20:07:04 +08:00
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choice
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prompt "Device type"
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2018-09-05 09:37:56 +08:00
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default SOC_STM32F401RC
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2017-11-17 20:07:04 +08:00
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config SOC_STM32F405RG
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bool "STM32F405RG"
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config SOC_STM32F405VG
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bool "STM32F405VG"
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config SOC_STM32F405ZG
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bool "STM32F405ZG"
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config SOC_STM32F415RG
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bool "STM32F415RG"
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config SOC_STM32F415VG
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bool "STM32F415VG"
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config SOC_STM32F415ZG
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bool "STM32F415ZG"
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config SOC_STM32F407VG
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bool "STM32F407VG"
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config SOC_STM32F407VE
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bool "STM32F407VE"
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config SOC_STM32F407ZG
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bool "STM32F407ZG"
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config SOC_STM32F407ZE
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bool "STM32F407ZE"
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config SOC_STM32F407IG
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bool "STM32F407IG"
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config SOC_STM32F407IE
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bool "STM32F407IE"
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config SOC_STM32F417VG
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bool "STM32F417VG"
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config SOC_STM32F417VE
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bool "STM32F417VE"
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config SOC_STM32F417ZG
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bool "STM32F417ZG"
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config SOC_STM32F417ZE
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bool "STM32F417ZE"
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config SOC_STM32F417IG
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bool "STM32F417IG"
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config SOC_STM32F417IE
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bool "STM32F417IE"
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config SOC_STM32F427VG
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bool "STM32F427VG"
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config SOC_STM32F427VI
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bool "STM32F427VI"
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config SOC_STM32F427ZG
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bool "STM32F427ZG"
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config SOC_STM32F427ZI
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bool "STM32F427ZI"
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config SOC_STM32F427IG
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bool "STM32F427IG"
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config SOC_STM32F427II
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bool "STM32F427II"
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config SOC_STM32F437VG
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bool "STM32F437VG"
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config SOC_STM32F437VI
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bool "STM32F437VI"
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config SOC_STM32F437ZG
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bool "STM32F437ZG"
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config SOC_STM32F437ZI
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bool "STM32F437ZI"
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config SOC_STM32F437IG
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bool "STM32F437IG"
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config SOC_STM32F437II
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bool "STM32F437II"
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config SOC_STM32F429VG
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bool "STM32F429VG"
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config SOC_STM32F429VI
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bool "STM32F429VI"
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config SOC_STM32F429ZG
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bool "STM32F429ZG"
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config SOC_STM32F429ZI
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bool "STM32F429ZI"
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config SOC_STM32F429BG
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bool "STM32F429BG"
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config SOC_STM32F429BI
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bool "STM32F429BI"
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config SOC_STM32F429NG
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bool "STM32F429NG"
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config SOC_STM32F429NI
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bool "STM32F429NI"
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config SOC_STM32F429IG
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bool "STM32F429IG"
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config SOC_STM32F429II
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bool "STM32F429II"
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config SOC_STM32F439VG
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bool "STM32F439VG"
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config SOC_STM32F439VI
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bool "STM32F439VI"
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config SOC_STM32F439ZG
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bool "STM32F439ZG"
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config SOC_STM32F439ZI
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bool "STM32F439ZI"
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config SOC_STM32F439BG
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bool "STM32F439BG"
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config SOC_STM32F439BI
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bool "STM32F439BI"
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config SOC_STM32F439NG
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bool "STM32F439NG"
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config SOC_STM32F439NI
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bool "STM32F439NI"
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config SOC_STM32F439IG
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bool "STM32F439IG"
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config SOC_STM32F439II
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bool "STM32F439II"
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config SOC_STM32F401CB
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bool "STM32F401CB"
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config SOC_STM32F401CC
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bool "STM32F401CC"
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config SOC_STM32F401RB
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bool "STM32F401RB"
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config SOC_STM32F401RC
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bool "STM32F401RC"
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config SOC_STM32F401VB
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bool "STM32F401VB"
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config SOC_STM32F401VC
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bool "STM32F401VC"
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config SOC_STM32F401CD
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bool "STM32F401CD"
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config SOC_STM32F401RD
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bool "STM32F401RD"
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config SOC_STM32F401VD
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bool "STM32F401VD"
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config SOC_STM32F401CE
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bool "STM32F401CE"
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config SOC_STM32F401RE
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bool "STM32F401RE"
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config SOC_STM32F401VE
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bool "STM32F401VE"
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config SOC_STM32F410T8
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bool "STM32F410T8"
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config SOC_STM32F410TB
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bool "STM32F410TB"
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config SOC_STM32F410C8
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bool "STM32F410C8"
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config SOC_STM32F410CB
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bool "STM32F410CB"
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config SOC_STM32F410R8
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bool "STM32F410R8"
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config SOC_STM32F410RB
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bool "STM32F410RB"
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config SOC_STM32F411CC
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bool "STM32F411CC"
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config SOC_STM32F411RC
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bool "STM32F411RC"
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config SOC_STM32F411VC
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bool "STM32F411VC"
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config SOC_STM32F411CE
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bool "STM32F411CE"
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config SOC_STM32F411RE
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bool "STM32F411RE"
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config SOC_STM32F411VE
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bool "STM32F411VE"
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config SOC_STM32F446MC
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bool "STM32F446MC"
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config SOC_STM32F446ME
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bool "STM32F446ME"
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config SOC_STM32F446RC
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bool "STM32F446RC"
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config SOC_STM32F446RE
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bool "STM32F446RE"
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config SOC_STM32F446VC
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bool "STM32F446VC"
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config SOC_STM32F446VE
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bool "STM32F446VE"
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config SOC_STM32F446ZC
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bool "STM32F446ZC"
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config SOC_STM32F446ZE
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bool "STM32F446ZE"
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config SOC_STM32F469AI
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bool "STM32F469AI"
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config SOC_STM32F469II
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bool "STM32F469II"
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config SOC_STM32F469BI
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bool "STM32F469BI"
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config SOC_STM32F469NI
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bool "STM32F469NI"
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config SOC_STM32F469AG
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bool "STM32F469AG"
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config SOC_STM32F469IG
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bool "STM32F469IG"
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config SOC_STM32F469BG
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bool "STM32F469BG"
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config SOC_STM32F469NG
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bool "STM32F469NG"
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config SOC_STM32F469AE
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bool "STM32F469AE"
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config SOC_STM32F469IE
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bool "STM32F469IE"
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config SOC_STM32F469BE
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bool "STM32F469BE"
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config SOC_STM32F469NE
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bool "STM32F469NE"
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config SOC_STM32F479AI
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bool "STM32F479AI"
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config SOC_STM32F479II
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bool "STM32F479II"
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config SOC_STM32F479BI
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bool "STM32F479BI"
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config SOC_STM32F479NI
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bool "STM32F479NI"
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config SOC_STM32F479AG
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bool "STM32F479AG"
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config SOC_STM32F479IG
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bool "STM32F479IG"
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config SOC_STM32F479BG
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bool "STM32F479BG"
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config SOC_STM32F479NG
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bool "STM32F479NG"
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config SOC_STM32F412CEU
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bool "STM32F412CEU"
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config SOC_STM32F412CGU
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bool "STM32F412CGU"
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config SOC_STM32F412ZET
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bool "STM32F412ZET"
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config SOC_STM32F412ZGT
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bool "STM32F412ZGT"
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config SOC_STM32F412ZEJ
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bool "STM32F412ZEJ"
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config SOC_STM32F412ZGJ
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bool "STM32F412ZGJ"
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config SOC_STM32F412VET
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bool "STM32F412VET"
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config SOC_STM32F412VGT
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bool "STM32F412VGT"
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config SOC_STM32F412VEH
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bool "STM32F412VEH"
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config SOC_STM32F412VGH
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bool "STM32F412VGH"
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config SOC_STM32F412RET
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bool "STM32F412RET"
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config SOC_STM32F412RGT
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bool "STM32F412RGT"
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config SOC_STM32F412REY
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bool "STM32F412REY"
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config SOC_STM32F412RGY
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bool "STM32F412RGY"
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config SOC_STM32F413CH
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bool "STM32F413CH"
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config SOC_STM32F413MH
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bool "STM32F413MH"
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config SOC_STM32F413RH
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bool "STM32F413RH"
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config SOC_STM32F413VH
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bool "STM32F413VH"
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config SOC_STM32F413ZH
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bool "STM32F413ZH"
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config SOC_STM32F413CG
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bool "STM32F413CG"
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config SOC_STM32F413MG
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bool "STM32F413MG"
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config SOC_STM32F413RG
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bool "STM32F413RG"
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config SOC_STM32F413VG
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bool "STM32F413VG"
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config SOC_STM32F413ZG
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bool "STM32F413ZG"
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config SOC_STM32F423CH
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bool "STM32F423CH"
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config SOC_STM32F423RH
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bool "STM32F423RH"
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config SOC_STM32F423VH
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bool "STM32F423VH"
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config SOC_STM32F423ZH
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bool "STM32F423ZH"
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endchoice
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config RT_USING_HSI
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bool "Using HSI as clock source"
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default n
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2018-07-05 17:11:53 +08:00
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config BSP_HSE_BY_PASS
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2018-07-14 19:42:44 +08:00
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bool "HSE Bypass"
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2018-07-05 17:11:53 +08:00
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depends on !RT_USING_HSI
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default n
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2017-11-17 20:07:04 +08:00
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config RT_HSE_VALUE
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int "HSE Value"
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default 8000000
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depends on !RT_USING_HSI
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2017-12-12 01:43:17 +08:00
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config RT_HSE_HCLK
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int "System Clock Value"
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default 84000000
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2018-10-11 18:09:31 +08:00
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config BSP_USING_UART1
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2017-11-17 20:07:04 +08:00
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bool "Using UART1"
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2018-10-11 18:09:31 +08:00
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select RT_USING_SERIAL
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2017-11-17 20:07:04 +08:00
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default y
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2018-10-11 18:09:31 +08:00
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config BSP_USING_UART2
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2017-11-17 20:07:04 +08:00
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bool "Using UART2"
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2018-10-11 18:09:31 +08:00
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select RT_USING_SERIAL
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2018-08-29 11:11:10 +08:00
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default n
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2018-10-11 18:09:31 +08:00
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config BSP_USING_UART3
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2018-08-29 11:11:10 +08:00
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bool "Using UART3"
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2018-10-11 18:09:31 +08:00
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select RT_USING_SERIAL
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2018-08-29 11:11:10 +08:00
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default n
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2018-10-11 18:09:31 +08:00
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config BSP_USING_UART6
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2017-11-17 20:07:04 +08:00
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bool "Using UART6"
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2018-10-11 18:09:31 +08:00
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select RT_USING_SERIAL
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2017-11-17 20:07:04 +08:00
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default n
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2018-08-12 20:08:44 +08:00
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if RT_USING_CAN
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config USING_BXCAN1
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bool "Enable CAN1 RX:PD0 TX:PD1. Do not select HDR."
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default n
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config USING_BXCAN2
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bool "Enable CAN2 RX:PB12 TX:PB6. Do not select HDR."
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default n
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endif
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2017-11-17 20:07:04 +08:00
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if RT_USING_SPI
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config RT_USING_SPI1
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bool "Using SPI1"
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default y
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config RT_USING_SPI2
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bool "Using SPI2"
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default n
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config RT_USING_SPI3
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bool "Using SPI3"
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default n
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endif
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2018-07-15 02:02:38 +08:00
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menuconfig BSP_USING_PWM1
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bool "Using PWM1"
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select RT_USING_PWM
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default n
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if BSP_USING_PWM1
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config BSP_USING_PWM1_CH1
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bool "Enable Channel 1 (PA8)"
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default n
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config BSP_USING_PWM1_CH2
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bool "Enable Channel 2 (PA9)"
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default n
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config BSP_USING_PWM1_CH3
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bool "Enable Channel 3 (PA10)"
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default n
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config BSP_USING_PWM1_CH4
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bool "Enable Channel 4 (PA11)"
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default n
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endif
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menuconfig BSP_USING_PWM2
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bool "Using PWM2"
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select RT_USING_PWM
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default n
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if BSP_USING_PWM2
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|
config BSP_USING_PWM2_CH1
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bool "Enable Channel 1 (PA5)"
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|
default n
|
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|
|
config BSP_USING_PWM2_CH2
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|
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bool "Enable Channel 2 (PB3)"
|
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|
default n
|
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|
|
config BSP_USING_PWM2_CH3
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|
|
bool "Enable Channel 3 (PB10)"
|
|
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|
|
default n
|
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|
|
config BSP_USING_PWM2_CH4
|
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bool "Enable Channel 4 (PA3)"
|
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|
default n
|
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|
|
endif
|
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|
|
menuconfig BSP_USING_PWM3
|
|
|
|
|
bool "Using PWM3"
|
|
|
|
|
select RT_USING_PWM
|
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|
|
|
default n
|
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|
|
|
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|
|
|
if BSP_USING_PWM3
|
|
|
|
|
config BSP_USING_PWM3_CH1
|
|
|
|
|
bool "Enable Channel 1 (PA6)"
|
|
|
|
|
default n
|
|
|
|
|
config BSP_USING_PWM3_CH2
|
|
|
|
|
bool "Enable Channel 2 (PA7)"
|
|
|
|
|
default n
|
|
|
|
|
config BSP_USING_PWM3_CH3
|
|
|
|
|
bool "Enable Channel 3 (PB0)"
|
|
|
|
|
default n
|
|
|
|
|
config BSP_USING_PWM3_CH4
|
|
|
|
|
bool "Enable Channel 4 (PB1)"
|
|
|
|
|
default n
|
|
|
|
|
endif
|
|
|
|
|
|
|
|
|
|
menuconfig BSP_USING_PWM4
|
|
|
|
|
bool "Using PWM4"
|
|
|
|
|
select RT_USING_PWM
|
|
|
|
|
default n
|
|
|
|
|
|
|
|
|
|
if BSP_USING_PWM4
|
|
|
|
|
config BSP_USING_PWM4_CH1
|
|
|
|
|
bool "Enable Channel 1 (PB6)"
|
|
|
|
|
default n
|
|
|
|
|
config BSP_USING_PWM4_CH2
|
|
|
|
|
bool "Enable Channel 2 (PB7)"
|
|
|
|
|
default n
|
|
|
|
|
config BSP_USING_PWM4_CH3
|
|
|
|
|
bool "Enable Channel 3 (PB8)"
|
|
|
|
|
default n
|
|
|
|
|
config BSP_USING_PWM4_CH4
|
|
|
|
|
bool "Enable Channel 4 (PB9)"
|
|
|
|
|
default n
|
|
|
|
|
endif
|
|
|
|
|
|
|
|
|
|
menuconfig BSP_USING_PWM5
|
|
|
|
|
bool "Using PWM5"
|
|
|
|
|
select RT_USING_PWM
|
|
|
|
|
default n
|
|
|
|
|
|
|
|
|
|
if BSP_USING_PWM5
|
|
|
|
|
config BSP_USING_PWM5_CH1
|
|
|
|
|
bool "Enable Channel 1 (PA0)"
|
|
|
|
|
default n
|
|
|
|
|
config BSP_USING_PWM5_CH2
|
|
|
|
|
bool "Enable Channel 2 (PA1)"
|
|
|
|
|
default n
|
|
|
|
|
config BSP_USING_PWM5_CH3
|
|
|
|
|
bool "Enable Channel 3 (PA2)"
|
|
|
|
|
default n
|
|
|
|
|
endif
|
|
|
|
|
|
2018-07-08 17:48:11 +08:00
|
|
|
if RT_USING_W25QXX || RT_USING_SFUD
|
|
|
|
|
config RT_FLASH_CS_PIN
|
|
|
|
|
int "SPI NOR Flash CS pin index"
|
2017-11-17 20:07:04 +08:00
|
|
|
default 0
|
2018-07-08 17:48:11 +08:00
|
|
|
config RT_FLASH_SPI_BUS_NAME
|
|
|
|
|
string "SPI NOR Flash Spi bus name"
|
2017-11-17 20:07:04 +08:00
|
|
|
default "spi1"
|
|
|
|
|
endif
|
|
|
|
|
|
2017-12-15 17:46:52 +08:00
|
|
|
if RT_USING_USB_HOST
|
|
|
|
|
menu "USB Host Config"
|
|
|
|
|
config USBH_USING_CONTROLLABLE_POWER
|
|
|
|
|
bool "using a gpio control usb power"
|
|
|
|
|
default y
|
|
|
|
|
if USBH_USING_CONTROLLABLE_POWER
|
|
|
|
|
config USBH_POWER_PIN
|
|
|
|
|
int "power control pin"
|
|
|
|
|
default 15
|
|
|
|
|
config USBH_CURRENT_PIN
|
|
|
|
|
int "current check pin"
|
|
|
|
|
default 86
|
|
|
|
|
endif
|
|
|
|
|
config USBH_USING_VBUS
|
|
|
|
|
bool "using vbus check pin"
|
|
|
|
|
default n
|
|
|
|
|
endmenu
|
|
|
|
|
endif
|
|
|
|
|
|
2017-11-17 20:07:04 +08:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2017-11-30 20:12:53 +08:00
|
|
|
|
