2017-09-15 18:10:51 +08:00
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//*****************************************************************************
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//
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// am_reg_wdt.h
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//! @file
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//!
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//! @brief Register macros for the WDT module
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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2018-09-21 16:10:44 +08:00
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// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
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2017-09-15 18:10:51 +08:00
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//
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//*****************************************************************************
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#ifndef AM_REG_WDT_H
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#define AM_REG_WDT_H
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//*****************************************************************************
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//
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// Instance finder. (1 instance(s) available)
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//
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//*****************************************************************************
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#define AM_REG_WDT_NUM_MODULES 1
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#define AM_REG_WDTn(n) \
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(REG_WDT_BASEADDR + 0x00000000 * n)
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//*****************************************************************************
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//
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// Register offsets.
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//
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//*****************************************************************************
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#define AM_REG_WDT_CFG_O 0x00000000
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#define AM_REG_WDT_RSTRT_O 0x00000004
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#define AM_REG_WDT_LOCK_O 0x00000008
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#define AM_REG_WDT_COUNT_O 0x0000000C
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#define AM_REG_WDT_INTEN_O 0x00000200
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#define AM_REG_WDT_INTSTAT_O 0x00000204
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#define AM_REG_WDT_INTCLR_O 0x00000208
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#define AM_REG_WDT_INTSET_O 0x0000020C
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//*****************************************************************************
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//
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// WDT_INTEN - WDT Interrupt register: Enable
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//
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//*****************************************************************************
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// Watchdog Timer Interrupt.
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#define AM_REG_WDT_INTEN_WDT_S 0
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#define AM_REG_WDT_INTEN_WDT_M 0x00000001
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#define AM_REG_WDT_INTEN_WDT(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// WDT_INTSTAT - WDT Interrupt register: Status
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//
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//*****************************************************************************
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// Watchdog Timer Interrupt.
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#define AM_REG_WDT_INTSTAT_WDT_S 0
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#define AM_REG_WDT_INTSTAT_WDT_M 0x00000001
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#define AM_REG_WDT_INTSTAT_WDT(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// WDT_INTCLR - WDT Interrupt register: Clear
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//
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//*****************************************************************************
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// Watchdog Timer Interrupt.
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#define AM_REG_WDT_INTCLR_WDT_S 0
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#define AM_REG_WDT_INTCLR_WDT_M 0x00000001
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#define AM_REG_WDT_INTCLR_WDT(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// WDT_INTSET - WDT Interrupt register: Set
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//
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//*****************************************************************************
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// Watchdog Timer Interrupt.
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#define AM_REG_WDT_INTSET_WDT_S 0
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#define AM_REG_WDT_INTSET_WDT_M 0x00000001
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#define AM_REG_WDT_INTSET_WDT(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// WDT_CFG - Configuration Register
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//
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//*****************************************************************************
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// Select the frequency for the WDT. All values not enumerated below are
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// undefined.
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#define AM_REG_WDT_CFG_CLKSEL_S 24
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#define AM_REG_WDT_CFG_CLKSEL_M 0x07000000
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#define AM_REG_WDT_CFG_CLKSEL(n) (((uint32_t)(n) << 24) & 0x07000000)
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#define AM_REG_WDT_CFG_CLKSEL_OFF 0x00000000
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#define AM_REG_WDT_CFG_CLKSEL_128HZ 0x01000000
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#define AM_REG_WDT_CFG_CLKSEL_16HZ 0x02000000
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#define AM_REG_WDT_CFG_CLKSEL_1HZ 0x03000000
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#define AM_REG_WDT_CFG_CLKSEL_1_16HZ 0x04000000
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// This bitfield is the compare value for counter bits 7:0 to generate a
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// watchdog interrupt.
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#define AM_REG_WDT_CFG_INTVAL_S 16
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#define AM_REG_WDT_CFG_INTVAL_M 0x00FF0000
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#define AM_REG_WDT_CFG_INTVAL(n) (((uint32_t)(n) << 16) & 0x00FF0000)
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// This bitfield is the compare value for counter bits 7:0 to generate a
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// watchdog reset.
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#define AM_REG_WDT_CFG_RESVAL_S 8
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#define AM_REG_WDT_CFG_RESVAL_M 0x0000FF00
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#define AM_REG_WDT_CFG_RESVAL(n) (((uint32_t)(n) << 8) & 0x0000FF00)
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// This bitfield enables the WDT reset.
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#define AM_REG_WDT_CFG_RESEN_S 2
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#define AM_REG_WDT_CFG_RESEN_M 0x00000004
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#define AM_REG_WDT_CFG_RESEN(n) (((uint32_t)(n) << 2) & 0x00000004)
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// This bitfield enables the WDT interrupt. Note : This bit must be set before
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// the interrupt status bit will reflect a watchdog timer expiration. The IER
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// interrupt register must also be enabled for a WDT interrupt to be sent to the
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// NVIC.
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#define AM_REG_WDT_CFG_INTEN_S 1
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#define AM_REG_WDT_CFG_INTEN_M 0x00000002
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#define AM_REG_WDT_CFG_INTEN(n) (((uint32_t)(n) << 1) & 0x00000002)
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// This bitfield enables the WDT.
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#define AM_REG_WDT_CFG_WDTEN_S 0
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#define AM_REG_WDT_CFG_WDTEN_M 0x00000001
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#define AM_REG_WDT_CFG_WDTEN(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// WDT_RSTRT - Restart the watchdog timer
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//
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//*****************************************************************************
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// Writing 0xB2 to WDTRSTRT restarts the watchdog timer.
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#define AM_REG_WDT_RSTRT_RSTRT_S 0
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#define AM_REG_WDT_RSTRT_RSTRT_M 0x000000FF
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#define AM_REG_WDT_RSTRT_RSTRT(n) (((uint32_t)(n) << 0) & 0x000000FF)
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#define AM_REG_WDT_RSTRT_RSTRT_KEYVALUE 0x000000B2
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//*****************************************************************************
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//
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// WDT_LOCK - Locks the WDT
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//
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//*****************************************************************************
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// Writing 0x3A locks the watchdog timer. Once locked, the WDTCFG reg cannot be
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// written and WDTEN is set.
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#define AM_REG_WDT_LOCK_LOCK_S 0
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#define AM_REG_WDT_LOCK_LOCK_M 0x000000FF
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#define AM_REG_WDT_LOCK_LOCK(n) (((uint32_t)(n) << 0) & 0x000000FF)
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#define AM_REG_WDT_LOCK_LOCK_KEYVALUE 0x0000003A
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//*****************************************************************************
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//
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// WDT_COUNT - Current Counter Value for WDT
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//
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//*****************************************************************************
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// Read-Only current value of the WDT counter
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#define AM_REG_WDT_COUNT_COUNT_S 0
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#define AM_REG_WDT_COUNT_COUNT_M 0x000000FF
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#define AM_REG_WDT_COUNT_COUNT(n) (((uint32_t)(n) << 0) & 0x000000FF)
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#endif // AM_REG_WDT_H
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