97 lines
4.6 KiB
C
97 lines
4.6 KiB
C
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/** @file reg_crc.h
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* @brief CRC Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the CRC driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_CRC_H__
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#define __REG_CRC_H__
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#include "sys_common.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Crc Register Frame Definition */
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/** @struct crcBase
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* @brief CRC Register Frame Definition
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*
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* This type is used to access the CRC Registers.
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*/
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/** @typedef crcBASE_t
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* @brief CRC Register Frame Type Definition
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*
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* This type is used to access the CRC Registers.
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*/
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typedef volatile struct crcBase
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{
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uint32 CTRL0; /**< 0x0000: Global Control Register 0 >**/
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uint32 rsvd1; /**< 0x0004: reserved >**/
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uint32 CTRL1; /**< 0x0008: Global Control Register 1 >**/
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uint32 rsvd2; /**< 0x000C: reserved >**/
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uint32 CTRL2; /**< 0x0010: Global Control Register 2 >**/
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uint32 rsvd3; /**< 0x0014: reserved >**/
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uint32 INTS; /**< 0x0018: Interrupt Enable Set Register >**/
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uint32 rsvd4; /**< 0x001C: reserved >**/
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uint32 INTR; /**< 0x0020: Interrupt Enable Reset Register >**/
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uint32 rsvd5; /**< 0x0024: reserved >**/
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uint32 STATUS; /**< 0x0028: Interrupt Status Register >**/
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uint32 rsvd6; /**< 0x002C: reserved >**/
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uint32 INT_OFFSET_REG; /**< 0x0030: Interrupt Offset >**/
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uint32 rsvd7; /**< 0x0034: reserved >**/
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uint32 BUSY; /**< 0x0038: CRC Busy Register >**/
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uint32 rsvd8; /**< 0x003C: reserved >**/
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uint32 PCOUNT_REG1; /**< 0x0040: Pattern Counter Preload Register1 >**/
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uint32 SCOUNT_REG1; /**< 0x0044: Sector Counter Preload Register1 >**/
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uint32 CURSEC_REG1; /**< 0x0048: Current Sector Register 1 >**/
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uint32 WDTOPLD1; /**< 0x004C: Channel 1 Watchdog Timeout Preload Register A >**/
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uint32 BCTOPLD1; /**< 0x0050: Channel 1 Block Complete Timeout Preload Register B >**/
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uint32 rsvd9[3]; /**< 0x0054: reserved >**/
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uint32 PSA_SIGREGL1; /**< 0x0060: Channel 1 PSA signature low register >**/
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uint32 PSA_SIGREGH1; /**< 0x0064: Channel 1 PSA signature high register >**/
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uint32 REGL1; /**< 0x0068: Channel 1 CRC value low register >**/
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uint32 REGH1; /**< 0x006C: Channel 1 CRC value high register >**/
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uint32 PSA_SECSIGREGL1; /**< 0x0070: Channel 1 PSA sector signature low register >**/
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uint32 PSA_SECSIGREGH1; /**< 0x0074: Channel 1 PSA sector signature high register >**/
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uint32 RAW_DATAREGL1; /**< 0x0078: Channel 1 Raw Data Low Register >**/
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uint32 RAW_DATAREGH1; /**< 0x007C: Channel 1 Raw Data High Register >**/
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uint32 PCOUNT_REG2; /**< 0x0080: CRC Pattern Counter Preload Register2 >**/
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uint32 SCOUNT_REG2; /**< 0x0084: Sector Counter Preload Register2 >**/
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uint32 CURSEC_REG2; /**< 0x0088: Current Sector Register 2>**/
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uint32 WDTOPLD2; /**< 0x008C: Channel 2 Watchdog Timeout Preload Register A >**/
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uint32 BCTOPLD2; /**< 0x0090: Channel 2 Block Complete Timeout Preload Register B >**/
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uint32 rsvd10[3]; /**< 0x0094: reserved >**/
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uint32 PSA_SIGREGL2; /**< 0x00A0: Channel 2 PSA signature low register >**/
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uint32 PSA_SIGREGH2; /**< 0x00A8: Channel 2 PSA signature high register >**/
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uint32 REGL2; /**< 0x00AC: Channel 2 CRC value low register >**/
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uint32 REGH2; /**< 0x00AC: Channel 2 CRC value high register >**/
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uint32 PSA_SECSIGREGL2; /**< 0x00B0: Channel 2 PSA sector signature low register >**/
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uint32 PSA_SECSIGREGH2; /**< 0x00B4: Channel 2 PSA sector signature high register >**/
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uint32 RAW_DATAREGL2; /**< 0x00B8: Channel 2 Raw Data Low Register >**/
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uint32 RAW_DATAREGH2; /**< 0x00BC: Channel 2 Raw Data High Register >**/
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}crcBASE_t;
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/** @def crcREG
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* @brief CRC Register Frame Pointer
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*
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* This pointer is used by the CRC driver to access the CRC registers.
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*/
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#define crcREG ((crcBASE_t *)0xFE000000U)
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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