83 lines
2.1 KiB
C
83 lines
2.1 KiB
C
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-02-22 airm2m first version
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*/
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#include "board.h"
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uint32_t SystemCoreClock;
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extern const uint32_t __isr_start_address;
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const uint32_t __attribute__((section (".app_info")))
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g_CAppInfo[256] =
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{
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__APP_START_MAGIC__,
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sizeof(g_CAppInfo),
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0,
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0,
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};
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void SystemInit(void)
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{
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#ifdef __USE_XTL__
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SYSCTRL->FREQ_SEL = 0x20000000 | SYSCTRL_FREQ_SEL_HCLK_DIV_1_2 | (1 << 13) | SYSCTRL_FREQ_SEL_CLOCK_SOURCE_EXT | SYSCTRL_FREQ_SEL_XTAL_192Mhz;
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#else
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SYSCTRL->FREQ_SEL = 0x20000000 | SYSCTRL_FREQ_SEL_HCLK_DIV_1_2 | (1 << 13) | SYSCTRL_FREQ_SEL_CLOCK_SOURCE_INC | SYSCTRL_FREQ_SEL_XTAL_192Mhz;
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#endif
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SCB->VTOR = (uint32_t)(&__isr_start_address);
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SYSCTRL->CG_CTRL1 = SYSCTRL_APBPeriph_ALL;
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SYSCTRL->SOFT_RST1 = SYSCTRL_APBPeriph_ALL;
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SYSCTRL->PHER_CTRL &= ~(1 << 20);
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SYSCTRL->SOFT_RST2 &= ~SYSCTRL_USB_RESET;
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SYSCTRL->LOCK_R |= SYSCTRL_USB_RESET;
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__enable_irq();
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}
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void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
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{
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SystemCoreClock = HSE_VALUE * (((SYSCTRL->FREQ_SEL & SYSCTRL_FREQ_SEL_XTAL_Mask) >> SYSCTRL_FREQ_SEL_XTAL_Pos) + 1);
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}
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void rt_hw_board_init(void)
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{
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GPIO_Config(GPIOC_03, 0, 0);
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GPIO_Config(GPIOD_14, 0, 0);
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GPIO_Config(GPIOD_15, 0, 0);
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__NVIC_SetPriorityGrouping(7 - __NVIC_PRIO_BITS);
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SystemCoreClockUpdate();
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#ifdef RT_USING_HEAP
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rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
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#endif
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rt_hw_systick_init();
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DMA_GlobalInit();
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Uart_GlobalInit();
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DMA_TakeStream(DMA1_STREAM_1);//for qspi
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CoreTick_Init();
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#ifdef RT_USING_PIN
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rt_hw_pin_init();
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#endif
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/* USART driver initialization is open by default */
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#ifdef RT_USING_SERIAL
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rt_hw_usart_init();
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#endif
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/* Set the shell console output device */
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#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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/* Board underlying hardware initialization */
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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}
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