113 lines
2.3 KiB
C
113 lines
2.3 KiB
C
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-16 bluebear233 first version
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*/
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#include <rtthread.h>
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#include "NuMicro.h"
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#include "drv_uart.h"
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#include "board.h"
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#ifdef __CC_ARM
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#elif __ICCARM__
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#pragma section="HEAP"
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#else
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extern int __bss_end;
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extern int __ram_top;
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#endif
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/**
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* This function will initial Clock tree.
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*/
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static void clock_init(void)
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{
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/* Unlock protected registers */
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SYS_UnlockReg();
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SystemInit();
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/* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */
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PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
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/* Enable External XTAL (4~24 MHz) */
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CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
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/* Waiting for 12MHz clock ready */
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CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk);
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/* Switch HCLK clock source to HXT */
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CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));
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/* Set core clock as PLL_CLOCK from PLL */
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CLK_SetCoreClock(FREQ_192MHZ);
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/* Set both PCLK0 and PCLK1 as HCLK/4 */
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CLK->PCLKDIV = CLK_PCLKDIV_PCLK0DIV4 | CLK_PCLKDIV_PCLK1DIV4;
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SystemCoreClockUpdate();
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/* Lock protected registers */
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SYS_LockReg();
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}
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/**
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* This function will initial M487 board.
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*/
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void rt_hw_board_init(void)
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{
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clock_init();
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#ifdef RT_USING_HEAP
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#ifdef __CC_ARM
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rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)SRAM_END);
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#elif __ICCARM__
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rt_system_heap_init(__segment_end("HEAP"), (void*)SRAM_END);
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#else
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/* init memory system */
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rt_system_heap_init((void*)&__bss_end, (void*)&__ram_top);
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#endif
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#endif /* RT_USING_HEAP */
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rt_hw_uart_init();
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#ifdef RT_USING_CONSOLE
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
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NVIC_SetPriorityGrouping(7);
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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}
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/**
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* This is the timer interrupt service routine.
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*
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*/
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void SysTick_Handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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void rt_hw_cpu_reset(void)
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{
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SYS_UnlockReg();
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SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
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}
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