483 lines
19 KiB
C
483 lines
19 KiB
C
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//*****************************************************************************
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// LPC5410x Microcontroller Startup code for use with LPCXpresso IDE
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//
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// Version : 141022
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//*****************************************************************************
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//
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// Copyright(C) NXP Semiconductors, 2014
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// All rights reserved.
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//
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// Software that is described herein is for illustrative purposes only
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// which provides customers with programming information regarding the
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// LPC products. This software is supplied "AS IS" without any warranties of
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// any kind, and NXP Semiconductors and its licensor disclaim any and
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// all warranties, express or implied, including all implied warranties of
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// merchantability, fitness for a particular purpose and non-infringement of
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// intellectual property rights. NXP Semiconductors assumes no responsibility
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// or liability for the use of the software, conveys no license or rights under any
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// patent, copyright, mask work right, or any other intellectual property rights in
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// or to any products. NXP Semiconductors reserves the right to make changes
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// in the software without notification. NXP Semiconductors also makes no
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// representation or warranty that such application will be suitable for the
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// specified use without further testing or modification.
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//
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// Permission to use, copy, modify, and distribute this software and its
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// documentation is hereby granted, under NXP Semiconductors' and its
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// licensor's relevant copyrights in the software, without fee, provided that it
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// is used in conjunction with NXP Semiconductors microcontrollers. This
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// copyright, permission, and disclaimer notice must appear in all copies of
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// this code.
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//*****************************************************************************
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#if defined (__cplusplus)
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#ifdef __REDLIB__
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#error Redlib does not support C++
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#else
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//*****************************************************************************
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//
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// The entry point for the C++ library startup
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//
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//*****************************************************************************
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extern "C" {
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extern void __libc_init_array(void);
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}
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#endif
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#endif
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#define WEAK __attribute__ ((weak))
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#define ALIAS(f) __attribute__ ((weak, alias (#f)))
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//*****************************************************************************
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#if defined (__cplusplus)
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extern "C" {
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#endif
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//*****************************************************************************
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#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
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// Declaration of external SystemInit function
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extern void SystemInit(void);
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#endif
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//*****************************************************************************
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//
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// Forward declaration of the default handlers. These are aliased.
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// When the application defines a handler (with the same name), this will
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// automatically take precedence over these weak definitions
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//
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//*****************************************************************************
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void ResetISR(void);
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#if defined (__MULTICORE_MASTER)
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void ResetISR2(void);
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#endif
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WEAK void NMI_Handler(void);
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WEAK void HardFault_Handler(void);
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WEAK void MemManage_Handler(void);
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WEAK void BusFault_Handler(void);
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WEAK void UsageFault_Handler(void);
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WEAK void SVC_Handler(void);
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WEAK void DebugMon_Handler(void);
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WEAK void PendSV_Handler(void);
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WEAK void SysTick_Handler(void);
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WEAK void IntDefaultHandler(void);
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//*****************************************************************************
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//
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// Forward declaration of the specific IRQ handlers. These are aliased
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// to the IntDefaultHandler, which is a 'forever' loop. When the application
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// defines a handler (with the same name), this will automatically take
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// precedence over these weak definitions
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//
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//*****************************************************************************
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// External Interrupts - Available on M0/M4
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void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
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void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
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void Reserved_IRQHandler(void) ALIAS(IntDefaultHandler);
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void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
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void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void PIN_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void PIN_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void PIN_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
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void PIN_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
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void UTICK_IRQHandler(void) ALIAS(IntDefaultHandler);
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void MRT_IRQHandler(void) ALIAS(IntDefaultHandler);
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void CT32B0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void CT32B1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void CT32B2_IRQHandler(void) ALIAS(IntDefaultHandler);
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void CT32B3_IRQHandler(void) ALIAS(IntDefaultHandler);
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void CT32B4_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SCT0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
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void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
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void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SPI0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SPI1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void ADC_SEQA_IRQHandler(void) ALIAS(IntDefaultHandler);
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void ADC_SEQB_IRQHandler(void) ALIAS(IntDefaultHandler);
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void ADC_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler);
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void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
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void MAILBOX_IRQHandler(void) ALIAS(IntDefaultHandler);
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// External Interrupts - For M4 only
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void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void PIN_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
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void PIN_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
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void PIN_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
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void PIN_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SPI2_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SPI3_IRQHandler(void) ALIAS(IntDefaultHandler);
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void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
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void Reserved41_IRQHandler(void) ALIAS(IntDefaultHandler);
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void Reserved42_IRQHandler(void) ALIAS(IntDefaultHandler);
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void Reserved43_IRQHandler(void) ALIAS(IntDefaultHandler);
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void Reserved44_IRQHandler(void) ALIAS(IntDefaultHandler);
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//*****************************************************************************
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//
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// The entry point for the application.
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// __main() is the entry point for Redlib based applications
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// main() is the entry point for Newlib based applications
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//
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//*****************************************************************************
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#if defined (__REDLIB__)
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extern void __main(void);
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#endif
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extern int main(void);
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//*****************************************************************************
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//
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// External declaration for the pointer to the stack top from the Linker Script
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//
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//*****************************************************************************
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extern void _vStackTop(void);
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//*****************************************************************************
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#if defined (__cplusplus)
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} // extern "C"
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#endif
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//*****************************************************************************
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//
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// The vector table.
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// This relies on the linker script to place at correct location in memory.
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//
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//*****************************************************************************
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extern void (* const g_pfnVectors[])(void);
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__attribute__ ((section(".isr_vector")))
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void (* const g_pfnVectors[])(void) = {
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// Core Level - CM3
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&_vStackTop, // The initial stack pointer
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ResetISR, // The reset handler
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NMI_Handler, // The NMI handler
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HardFault_Handler, // The hard fault handler
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MemManage_Handler, // The MPU fault handler
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BusFault_Handler, // The bus fault handler
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UsageFault_Handler, // The usage fault handler
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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SVC_Handler, // SVCall handler
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DebugMon_Handler, // Debug monitor handler
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0, // Reserved
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PendSV_Handler, // The PendSV handler
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SysTick_Handler, // The SysTick handler
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// External Interrupts - Available on M0/M4
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WDT_IRQHandler, // Watchdog
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BOD_IRQHandler, // Brown Out Detect
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Reserved_IRQHandler, // Reserved
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DMA_IRQHandler, // DMA Controller
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GINT0_IRQHandler, // GPIO Group0 Interrupt
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PIN_INT0_IRQHandler, // PIO INT0
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PIN_INT1_IRQHandler, // PIO INT1
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PIN_INT2_IRQHandler, // PIO INT2
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PIN_INT3_IRQHandler, // PIO INT3
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UTICK_IRQHandler, // UTICK timer
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MRT_IRQHandler, // Multi-Rate Timer
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CT32B0_IRQHandler, // Counter Timer 0
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CT32B1_IRQHandler, // Counter Timer 1
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CT32B2_IRQHandler, // Counter Timer 2
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CT32B3_IRQHandler, // Counter Timer 3
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CT32B4_IRQHandler, // Counter Timer 4
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SCT0_IRQHandler, // Smart Counter Timer
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UART0_IRQHandler, // UART0
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UART1_IRQHandler, // UART1
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UART2_IRQHandler, // UART2
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UART3_IRQHandler, // UART3
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I2C0_IRQHandler, // I2C0 controller
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I2C1_IRQHandler, // I2C1 controller
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I2C2_IRQHandler, // I2C2 controller
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SPI0_IRQHandler, // SPI0 controller
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SPI1_IRQHandler, // SPI1 controller
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ADC_SEQA_IRQHandler, // ADC SEQA
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ADC_SEQB_IRQHandler, // ADC SEQB
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ADC_THCMP_IRQHandler, // ADC THCMP and OVERRUN ORed
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RTC_IRQHandler, // RTC Timer
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Reserved_IRQHandler, // Reserved
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MAILBOX_IRQHandler, // Mailbox
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// External Interrupts - For M4 only
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GINT1_IRQHandler, // GPIO Group1 Interrupt
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PIN_INT4_IRQHandler, // PIO INT4
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PIN_INT5_IRQHandler, // PIO INT5
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PIN_INT6_IRQHandler, // PIO INT6
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PIN_INT7_IRQHandler, // PIO INT7
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SPI2_IRQHandler, // SPI2 controller
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SPI3_IRQHandler, // SPI3 controller
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0, // Reserved
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RIT_IRQHandler, // RIT Timer
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Reserved41_IRQHandler, // Reserved
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Reserved42_IRQHandler, // Reserved
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Reserved43_IRQHandler, // Reserved
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Reserved44_IRQHandler, // Reserved
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}; /* End of g_pfnVectors */
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//*****************************************************************************
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// Functions to carry out the initialization of RW and BSS data sections. These
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// are written as separate functions rather than being inlined within the
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// ResetISR() function in order to cope with MCUs with multiple banks of
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// memory.
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//*****************************************************************************
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__attribute__ ((section(".after_vectors")))
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void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
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unsigned int *pulDest = (unsigned int*) start;
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unsigned int *pulSrc = (unsigned int*) romstart;
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unsigned int loop;
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for (loop = 0; loop < len; loop = loop + 4)
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*pulDest++ = *pulSrc++;
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}
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__attribute__ ((section(".after_vectors")))
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void bss_init(unsigned int start, unsigned int len) {
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unsigned int *pulDest = (unsigned int*) start;
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unsigned int loop;
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for (loop = 0; loop < len; loop = loop + 4)
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*pulDest++ = 0;
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}
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//*****************************************************************************
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// The following symbols are constructs generated by the linker, indicating
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// the location of various points in the "Global Section Table". This table is
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// created by the linker via the Code Red managed linker script mechanism. It
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// contains the load address, execution address and length of each RW data
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// section and the execution and length of each BSS (zero initialized) section.
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//*****************************************************************************
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extern unsigned int __data_section_table;
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extern unsigned int __data_section_table_end;
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extern unsigned int __bss_section_table;
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extern unsigned int __bss_section_table_end;
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//*****************************************************************************
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// Reset entry point for your code.
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// Sets up a simple runtime environment and initializes the C/C++
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// library.
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//*****************************************************************************
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#if defined (__MULTICORE_MASTER)
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//#define cpu_ctrl 0x40000300
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//#define coproc_boot 0x40000304
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//#define set coproc_stack 0x40000308
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__attribute__ ((naked, section(".after_vectors.reset")))
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void ResetISR(void) {
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asm volatile(
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".set cpu_ctrl, 0x40000300\t\n"
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".set coproc_boot, 0x40000304\t\n"
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".set coproc_stack, 0x40000308\t\n"
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"MOVS R5, #1\t\n"
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"LDR R0, =0xE000ED00\t\n"
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"LDR R1, [R0]\t\n" // READ CPUID register
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"LDR R2,=0x410CC601\t\n" // CM0 R0p1 identifier
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"EORS R1,R1,R2\t\n" // XOR to see if we are C0
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"LDR R3, =cpu_ctrl\t\n" // get address of CPU_CTRL
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"LDR R1,[R3]\t\n" // read cpu_ctrl reg into R1
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"BEQ.N cm0_boot\t\n"
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"cm4_boot:\t\n"
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"LDR R0,=coproc_boot\t\n" // coproc boot address
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"LDR R0,[R0]\t\n" // get address to branch to
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"MOVS R0,R0\t\n" // Check if 0
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"BEQ.N check_master_m4\t\n" // if zero in boot reg, we just branch to real reset
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"BX R0\t\n" // otherwise, we branch to boot address
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"commonboot:\t\n"
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"LDR R0, =ResetISR2\t\n" // Jump to 'real' reset handler
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"BX R0\t\n"
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"cm0_boot:\t\n"
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"LDR R0,=coproc_boot\t\n" // coproc boot address
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"LDR R0,[R0]\t\n" // get address to branch to
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"MOVS R0,R0\t\n" // Check if 0
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"BEQ.N check_master_m0\t\n" // if zero in boot reg, we just branch to real reset
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"LDR R1,=coproc_stack\t\n" // pickup coprocesor stackpointer (from syscon CPSTACK)
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"LDR R1,[R1]\t\n"
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"MOV SP,R1\t\n"
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"BX R0\t\n" // goto boot address
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"check_master_m0:\t\n"
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"ANDS R1,R1,R5\t\n" // bit test bit0
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"BEQ.N commonboot\t\n" // if we get 0, that means we are masters
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"B.N goto_sleep_pending_reset\t\n" // Otherwise, there is no startup vector for slave, so we go to sleep
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"check_master_m4:\t\n"
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"ANDS R1,R1,R5\t\n" // bit test bit0
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"BNE.N commonboot\t\n" // if we get 1, that means we are masters
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"goto_sleep_pending_reset:\t\n"
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"MOV SP,R5\t\n" // load 0x1 into SP so that any stacking (eg on NMI) will not cause us to wakeup
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// and write to uninitialised Stack area (instead it will LOCK us up before we cause damage)
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// this code should only be reached if debugger bypassed ROM or we changed master without giving
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// correct start address, the only way out of this is through a debugger change of SP and PC
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"sleepo:\t\n"
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"WFI\t\n" // go to sleep
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"B.N sleepo\t\n"
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);
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}
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__attribute__ ((section(".after_vectors.reset")))
|
||
|
|
void ResetISR2(void) {
|
||
|
|
|
||
|
|
#else
|
||
|
|
__attribute__ ((section(".after_vectors.reset")))
|
||
|
|
void ResetISR(void) {
|
||
|
|
#endif
|
||
|
|
|
||
|
|
// If this is not the CM0+ core...
|
||
|
|
#if !defined (CORE_M0PLUS)
|
||
|
|
// If this is not a slave project...
|
||
|
|
#if !defined (__MULTICORE_M0SLAVE) && \
|
||
|
|
!defined (__MULTICORE_M4SLAVE)
|
||
|
|
// Optionally enable RAM banks that may be off by default at reset
|
||
|
|
#if !defined (DONT_ENABLE_DISABLED_RAMBANKS)
|
||
|
|
volatile unsigned int *SYSCON_SYSAHBCLKCTRL0 = (unsigned int *) 0x400000c0;
|
||
|
|
// Ensure that SRAM2(4) bit in SYSAHBCLKCTRL0 are set
|
||
|
|
*SYSCON_SYSAHBCLKCTRL0 |= (1 << 4);
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
//
|
||
|
|
// Copy the data sections from flash to SRAM.
|
||
|
|
//
|
||
|
|
unsigned int LoadAddr, ExeAddr, SectionLen;
|
||
|
|
unsigned int *SectionTableAddr;
|
||
|
|
|
||
|
|
// Load base address of Global Section Table
|
||
|
|
SectionTableAddr = &__data_section_table;
|
||
|
|
|
||
|
|
// Copy the data sections from flash to SRAM.
|
||
|
|
while (SectionTableAddr < &__data_section_table_end) {
|
||
|
|
LoadAddr = *SectionTableAddr++;
|
||
|
|
ExeAddr = *SectionTableAddr++;
|
||
|
|
SectionLen = *SectionTableAddr++;
|
||
|
|
data_init(LoadAddr, ExeAddr, SectionLen);
|
||
|
|
}
|
||
|
|
// At this point, SectionTableAddr = &__bss_section_table;
|
||
|
|
// Zero fill the bss segment
|
||
|
|
while (SectionTableAddr < &__bss_section_table_end) {
|
||
|
|
ExeAddr = *SectionTableAddr++;
|
||
|
|
SectionLen = *SectionTableAddr++;
|
||
|
|
bss_init(ExeAddr, SectionLen);
|
||
|
|
}
|
||
|
|
|
||
|
|
#if !defined (__USE_LPCOPEN)
|
||
|
|
// LPCOpen init code deals with FP and VTOR initialisation
|
||
|
|
#if defined (__VFP_FP__) && !defined (__SOFTFP__)
|
||
|
|
/*
|
||
|
|
* Code to enable the Cortex-M4 FPU only included
|
||
|
|
* if appropriate build options have been selected.
|
||
|
|
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
|
||
|
|
*/
|
||
|
|
// CPACR is located at address 0xE000ED88
|
||
|
|
asm("LDR.W R0, =0xE000ED88");
|
||
|
|
// Read CPACR
|
||
|
|
asm("LDR R1, [R0]");
|
||
|
|
// Set bits 20-23 to enable CP10 and CP11 coprocessors
|
||
|
|
asm(" ORR R1, R1, #(0xF << 20)");
|
||
|
|
// Write back the modified value to the CPACR
|
||
|
|
asm("STR R1, [R0]");
|
||
|
|
#endif // (__VFP_FP__) && !(__SOFTFP__)
|
||
|
|
// ******************************
|
||
|
|
// Check to see if we are running the code from a non-zero
|
||
|
|
// address (eg RAM, external flash), in which case we need
|
||
|
|
// to modify the VTOR register to tell the CPU that the
|
||
|
|
// vector table is located at a non-0x0 address.
|
||
|
|
|
||
|
|
// Note that we do not use the CMSIS register access mechanism,
|
||
|
|
// as there is no guarantee that the project has been configured
|
||
|
|
// to use CMSIS.
|
||
|
|
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
|
||
|
|
if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) {
|
||
|
|
// CMSIS : SCB->VTOR = <address of vector table>
|
||
|
|
*pSCB_VTOR = (unsigned int) g_pfnVectors;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
|
||
|
|
SystemInit();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined (__cplusplus)
|
||
|
|
//
|
||
|
|
// Call C++ library initialisation
|
||
|
|
//
|
||
|
|
__libc_init_array();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined (__REDLIB__)
|
||
|
|
// Call the Redlib library, which in turn calls main()
|
||
|
|
__main();
|
||
|
|
#else
|
||
|
|
main();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
//
|
||
|
|
// main() shouldn't return, but if it does, we'll just enter an infinite loop
|
||
|
|
//
|
||
|
|
while (1) {
|
||
|
|
;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
// Default exception handlers. Override the ones here by defining your own
|
||
|
|
// handler routines in your application code.
|
||
|
|
//*****************************************************************************
|
||
|
|
__attribute__ ((section(".after_vectors")))
|
||
|
|
void NMI_Handler(void) {
|
||
|
|
while (1) {
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
__attribute__ ((section(".after_vectors")))
|
||
|
|
void HardFault_Handler(void) {
|
||
|
|
while (1) {
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
__attribute__ ((section(".after_vectors")))
|
||
|
|
void SVC_Handler(void) {
|
||
|
|
while (1) {
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
__attribute__ ((section(".after_vectors")))
|
||
|
|
void PendSV_Handler(void) {
|
||
|
|
while (1) {
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
__attribute__ ((section(".after_vectors")))
|
||
|
|
void SysTick_Handler(void) {
|
||
|
|
while (1) {
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// Processor ends up here if an unexpected interrupt occurs or a specific
|
||
|
|
// handler is not present in the application code.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
__attribute__ ((section(".after_vectors")))
|
||
|
|
void IntDefaultHandler(void) {
|
||
|
|
while (1) {
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|