2017-09-15 18:10:51 +08:00
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//*****************************************************************************
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//
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// am_hal_ctimer.h
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//! @file
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//!
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//! @brief Functions for accessing and configuring the CTIMER.
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//!
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//! @addtogroup ctimer2 Counter/Timer (CTIMER)
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//! @ingroup apollo2hal
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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2018-09-21 16:10:44 +08:00
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// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
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2017-09-15 18:10:51 +08:00
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//
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//*****************************************************************************
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#ifndef AM_HAL_CTIMER_H
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#define AM_HAL_CTIMER_H
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//*****************************************************************************
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//
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//! Number of timers
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//
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//*****************************************************************************
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#define AM_HAL_CTIMER_TIMERS_NUM 4
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//*****************************************************************************
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//
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//! Timer offset value
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//
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//*****************************************************************************
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#define AM_HAL_CTIMER_TIMER_OFFSET (AM_REG_CTIMER_TMR1_O - AM_REG_CTIMER_TMR0_O)
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//*****************************************************************************
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//
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//! @name Interrupt Status Bits
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//! @brief Interrupt Status Bits for enable/disble use
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//!
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//! These macros may be used to set and clear interrupt bits
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_CTIMER_INT_TIMERA0C0 AM_REG_CTIMER_INTEN_CTMRA0C0INT_M
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#define AM_HAL_CTIMER_INT_TIMERA0C1 AM_REG_CTIMER_INTEN_CTMRA0C1INT_M
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#define AM_HAL_CTIMER_INT_TIMERA1C0 AM_REG_CTIMER_INTEN_CTMRA1C0INT_M
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#define AM_HAL_CTIMER_INT_TIMERA1C1 AM_REG_CTIMER_INTEN_CTMRA1C1INT_M
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#define AM_HAL_CTIMER_INT_TIMERA2C0 AM_REG_CTIMER_INTEN_CTMRA2C0INT_M
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#define AM_HAL_CTIMER_INT_TIMERA2C1 AM_REG_CTIMER_INTEN_CTMRA2C1INT_M
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#define AM_HAL_CTIMER_INT_TIMERA3C0 AM_REG_CTIMER_INTEN_CTMRA3C0INT_M
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#define AM_HAL_CTIMER_INT_TIMERA3C1 AM_REG_CTIMER_INTEN_CTMRA3C1INT_M
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#define AM_HAL_CTIMER_INT_TIMERB0C0 AM_REG_CTIMER_INTEN_CTMRB0C0INT_M
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#define AM_HAL_CTIMER_INT_TIMERB0C1 AM_REG_CTIMER_INTEN_CTMRB0C1INT_M
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#define AM_HAL_CTIMER_INT_TIMERB1C0 AM_REG_CTIMER_INTEN_CTMRB1C0INT_M
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#define AM_HAL_CTIMER_INT_TIMERB1C1 AM_REG_CTIMER_INTEN_CTMRB1C1INT_M
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#define AM_HAL_CTIMER_INT_TIMERB2C0 AM_REG_CTIMER_INTEN_CTMRB2C0INT_M
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#define AM_HAL_CTIMER_INT_TIMERB2C1 AM_REG_CTIMER_INTEN_CTMRB2C1INT_M
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#define AM_HAL_CTIMER_INT_TIMERB3C0 AM_REG_CTIMER_INTEN_CTMRB3C0INT_M
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#define AM_HAL_CTIMER_INT_TIMERB3C1 AM_REG_CTIMER_INTEN_CTMRB3C1INT_M
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//
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// Deprecated, use the newer macros above.
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//
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#define AM_HAL_CTIMER_INT_TIMERA0 AM_HAL_CTIMER_INT_TIMERA0C0
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#define AM_HAL_CTIMER_INT_TIMERB0 AM_HAL_CTIMER_INT_TIMERB0C0
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#define AM_HAL_CTIMER_INT_TIMERA1 AM_HAL_CTIMER_INT_TIMERA1C0
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#define AM_HAL_CTIMER_INT_TIMERB1 AM_HAL_CTIMER_INT_TIMERB1C0
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#define AM_HAL_CTIMER_INT_TIMERA2 AM_HAL_CTIMER_INT_TIMERA2C0
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#define AM_HAL_CTIMER_INT_TIMERB2 AM_HAL_CTIMER_INT_TIMERB2C0
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#define AM_HAL_CTIMER_INT_TIMERA3 AM_HAL_CTIMER_INT_TIMERA3C0
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#define AM_HAL_CTIMER_INT_TIMERB3 AM_HAL_CTIMER_INT_TIMERB3C0
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//! @}
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//*****************************************************************************
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//
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//! @name Configuration options
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//! @brief Configuration options for \e am_hal_ctimer_config_t
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//!
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//! These options are to be used with the \e am_hal_ctimer_config_t structure
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//! used by \e am_hal_ctimer_config
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2018-09-21 16:10:44 +08:00
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//! @{
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2017-09-15 18:10:51 +08:00
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//
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//*****************************************************************************
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#define AM_HAL_CTIMER_CLK_PIN AM_REG_CTIMER_CTRL0_TMRA0CLK(0x0)
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#define AM_HAL_CTIMER_HFRC_12MHZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x1)
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#define AM_HAL_CTIMER_HFRC_3MHZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x2)
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#define AM_HAL_CTIMER_HFRC_187_5KHZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x3)
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#define AM_HAL_CTIMER_HFRC_47KHZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x4)
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#define AM_HAL_CTIMER_HFRC_12KHZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x5)
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#define AM_HAL_CTIMER_XT_32_768KHZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x6)
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#define AM_HAL_CTIMER_XT_16_384KHZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x7)
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#define AM_HAL_CTIMER_XT_2_048KHZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x8)
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#define AM_HAL_CTIMER_XT_256HZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0x9)
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#define AM_HAL_CTIMER_LFRC_512HZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0xA)
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#define AM_HAL_CTIMER_LFRC_32HZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0xB)
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#define AM_HAL_CTIMER_LFRC_1HZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0xC)
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#define AM_HAL_CTIMER_LFRC_1_16HZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0xD)
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#define AM_HAL_CTIMER_RTC_100HZ AM_REG_CTIMER_CTRL0_TMRA0CLK(0xE)
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#define AM_HAL_CTIMER_HCLK AM_REG_CTIMER_CTRL0_TMRA0CLK(0xF)
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#define AM_HAL_CTIMER_BUCK AM_REG_CTIMER_CTRL0_TMRA0CLK(0x10)
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//! @}
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//*****************************************************************************
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//
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// Timer function macros.
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//
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//*****************************************************************************
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#define AM_HAL_CTIMER_FN_ONCE AM_REG_CTIMER_CTRL0_TMRA0FN(0)
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#define AM_HAL_CTIMER_FN_REPEAT AM_REG_CTIMER_CTRL0_TMRA0FN(1)
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#define AM_HAL_CTIMER_FN_PWM_ONCE AM_REG_CTIMER_CTRL0_TMRA0FN(2)
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#define AM_HAL_CTIMER_FN_PWM_REPEAT AM_REG_CTIMER_CTRL0_TMRA0FN(3)
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#define AM_HAL_CTIMER_FN_CONTINUOUS AM_REG_CTIMER_CTRL0_TMRA0FN(4)
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//*****************************************************************************
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//
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// Half-timer options.
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//
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//*****************************************************************************
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#define AM_HAL_CTIMER_INT_ENABLE AM_REG_CTIMER_CTRL0_TMRA0IE0_M
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#define AM_HAL_CTIMER_PIN_ENABLE AM_REG_CTIMER_CTRL0_TMRA0PE_M
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#define AM_HAL_CTIMER_PIN_INVERT AM_REG_CTIMER_CTRL0_TMRA0POL_M
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#define AM_HAL_CTIMER_CLEAR AM_REG_CTIMER_CTRL0_TMRA0CLR_M
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//*****************************************************************************
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//
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// Additional timer options.
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//
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//*****************************************************************************
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#define AM_HAL_CTIMER_LINK AM_REG_CTIMER_CTRL0_CTLINK0_M
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#define AM_HAL_CTIMER_ADC_TRIG AM_REG_CTIMER_CTRL3_ADCEN_M
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//*****************************************************************************
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//
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// Timer selection macros.
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//
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//*****************************************************************************
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#define AM_HAL_CTIMER_TIMERA 0x0000FFFF
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#define AM_HAL_CTIMER_TIMERB 0xFFFF0000
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#define AM_HAL_CTIMER_BOTH 0xFFFFFFFF
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//! @}
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//*****************************************************************************
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//
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// Timer configuration structure
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//
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//*****************************************************************************
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typedef struct
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{
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//
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//! Set to 1 to operate this timer as a 32-bit timer instead of two 16-bit
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//! timers.
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//
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uint32_t ui32Link;
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//
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//! Configuration options for TIMERA
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//
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uint32_t ui32TimerAConfig;
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//
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//! Configuration options for TIMERB
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//
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uint32_t ui32TimerBConfig;
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}
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am_hal_ctimer_config_t;
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//*****************************************************************************
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//
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// Function pointer type for CTimer interrupt handlers.
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//
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//*****************************************************************************
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typedef void (*am_hal_ctimer_handler_t)(void);
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2018-09-21 16:10:44 +08:00
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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2017-09-15 18:10:51 +08:00
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//*****************************************************************************
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//
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// External function definitions
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//
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//*****************************************************************************
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extern void am_hal_ctimer_config(uint32_t ui32TimerNumber,
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am_hal_ctimer_config_t *psConfig);
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extern void am_hal_ctimer_config_single(uint32_t ui32TimerNumber,
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uint32_t ui32TimerSegment,
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uint32_t ui32ConfigVal);
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extern void am_hal_ctimer_start(uint32_t ui32TimerNumber,
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uint32_t ui32TimerSegment);
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extern void am_hal_ctimer_stop(uint32_t ui32TimerNumber,
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uint32_t ui32TimerSegment);
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extern void am_hal_ctimer_clear(uint32_t ui32TimerNumber,
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uint32_t ui32TimerSegment);
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extern uint32_t am_hal_ctimer_read(uint32_t ui32TimerNumber,
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uint32_t ui32TimerSegment);
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extern void am_hal_ctimer_pin_enable(uint32_t ui32TimerNumber,
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uint32_t ui32TimerSegment);
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extern void am_hal_ctimer_pin_disable(uint32_t ui32TimerNumber,
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uint32_t ui32TimerSegment);
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extern void am_hal_ctimer_pin_invert(uint32_t ui32TimerNumber,
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uint32_t ui32TimerSegment,
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bool bInvertOutput);
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extern void am_hal_ctimer_compare_set(uint32_t ui32TimerNumber,
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uint32_t ui32TimerSegment,
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uint32_t ui32CompareReg,
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uint32_t ui32Value);
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extern void am_hal_ctimer_period_set(uint32_t ui32TimerNumber,
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uint32_t ui32TimerSegment,
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uint32_t ui32Period,
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uint32_t ui32OnTime);
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extern void am_hal_ctimer_adc_trigger_enable(void);
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extern void am_hal_ctimer_adc_trigger_disable(void);
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extern void am_hal_ctimer_int_enable(uint32_t ui32Interrupt);
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extern uint32_t am_hal_ctimer_int_enable_get(void);
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extern void am_hal_ctimer_int_disable(uint32_t ui32Interrupt);
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extern void am_hal_ctimer_int_set(uint32_t ui32Interrupt);
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extern void am_hal_ctimer_int_clear(uint32_t ui32Interrupt);
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extern uint32_t am_hal_ctimer_int_status_get(bool bEnabledOnly);
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extern void am_hal_ctimer_int_register(uint32_t ui32Interrupt,
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am_hal_ctimer_handler_t pfnHandler);
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extern void am_hal_ctimer_int_service(uint32_t ui32Status);
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#ifdef __cplusplus
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}
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#endif
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#endif // AM_HAL_CTIMER_H
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//*****************************************************************************
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//
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// End Doxygen group.
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//! @}
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//
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//*****************************************************************************
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