285 lines
8.4 KiB
C
285 lines
8.4 KiB
C
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/*
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* File : x1000.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2015-11-19 Urey the first version
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*/
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#ifndef __X1000_H__
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#define __X1000_H__
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#include "../common/mips.h"
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#ifndef __ASSEMBLY__
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#define cache_unroll(base,op) \
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__asm__ __volatile__(" \
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.set noreorder; \
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.set mips3; \
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cache %1, (%0); \
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.set mips0; \
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.set reorder" \
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: \
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: "r" (base), \
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"i" (op));
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/* cpu pipeline flush */
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static inline void jz_sync(void)
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{
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__asm__ volatile ("sync");
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}
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static inline void writeb(u8 value, u32 address)
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{
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*((volatile u8 *) address) = value;
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}
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static inline void writew( u16 value, u32 address)
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{
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*((volatile u16 *) address) = value;
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}
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static inline void writel(u32 value, u32 address)
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{
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*((volatile u32 *) address) = value;
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}
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static inline u8 readb(u32 address)
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{
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return *((volatile u8 *)address);
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}
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static inline u16 readw(u32 address)
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{
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return *((volatile u16 *)address);
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}
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static inline u32 readl(u32 address)
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{
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return *((volatile u32 *)address);
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}
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static inline void jz_writeb(u32 address, u8 value)
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{
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*((volatile u8 *)address) = value;
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}
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static inline void jz_writew(u32 address, u16 value)
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{
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*((volatile u16 *)address) = value;
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}
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static inline void jz_writel(u32 address, u32 value)
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{
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*((volatile u32 *)address) = value;
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}
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static inline u8 jz_readb(u32 address)
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{
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return *((volatile u8 *)address);
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}
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static inline u16 jz_readw(u32 address)
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{
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return *((volatile u16 *)address);
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}
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static inline u32 jz_readl(u32 address)
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{
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return *((volatile u32 *)address);
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}
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#define BIT(n) (0x01u << (n))
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#define BIT0 (0x01u << 0)
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#define BIT1 (0x01u << 1)
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#define BIT2 (0x01u << 2)
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#define BIT3 (0x01u << 3)
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#define BIT4 (0x01u << 4)
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#define BIT5 (0x01u << 5)
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#define BIT6 (0x01u << 6)
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#define BIT7 (0x01u << 7)
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#define BIT8 (0x01u << 8)
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#define BIT9 (0x01u << 9)
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#define BIT10 (0x01u << 10)
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#define BIT11 (0x01u << 11)
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#define BIT12 (0x01u << 12)
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#define BIT13 (0x01u << 13)
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#define BIT14 (0x01u << 14)
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#define BIT15 (0x01u << 15)
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#define BIT16 (0x01u << 16)
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#define BIT17 (0x01u << 17)
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#define BIT18 (0x01u << 18)
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#define BIT19 (0x01u << 19)
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#define BIT20 (0x01u << 20)
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#define BIT21 (0x01u << 21)
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#define BIT22 (0x01u << 22)
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#define BIT23 (0x01u << 23)
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#define BIT24 (0x01u << 24)
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#define BIT25 (0x01u << 25)
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#define BIT26 (0x01u << 26)
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#define BIT27 (0x01u << 27)
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#define BIT28 (0x01u << 28)
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#define BIT29 (0x01u << 29)
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#define BIT30 (0x01u << 30)
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#define BIT31 (0x01u << 31)
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/* Generate the bit field mask from msb to lsb */
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#define BITS_H2L(msb, lsb) ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))
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/* Get the bit field value from the data which is read from the register */
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#define get_bf_value(data, lsb, mask) (((data) & (mask)) >> (lsb))
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#endif /* !ASSEMBLY */
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//----------------------------------------------------------------------
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// Register Definitions
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//
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/* AHB0 BUS Devices Base */
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#define HARB0_BASE 0xB3000000
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#define EMC_BASE 0xB3010000
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#define DDRC_BASE 0xB3020000
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#define MDMAC_BASE 0xB3030000
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#define LCD_BASE 0xB3050000
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#define TVE_BASE 0xB3050000
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#define SLCD_BASE 0xB3050000
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#define CIM_BASE 0xB3060000
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#define IPU_BASE 0xB3080000
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/* AHB1 BUS Devices Base */
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#define HARB1_BASE 0xB3200000
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#define DMAGP0_BASE 0xB3210000
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#define DMAGP1_BASE 0xB3220000
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#define DMAGP2_BASE 0xB3230000
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#define MC_BASE 0xB3250000
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#define ME_BASE 0xB3260000
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#define DEBLK_BASE 0xB3270000
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#define IDCT_BASE 0xB3280000
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#define CABAC_BASE 0xB3290000
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#define TCSM0_BASE 0xB32B0000
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#define TCSM1_BASE 0xB32C0000
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#define SRAM_BASE 0xB32D0000
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/* AHB2 BUS Devices Base */
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#define HARB2_BASE 0xB3400000
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#define NEMC_BASE 0xB3410000
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#define DMAC_BASE 0xB3420000
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#define UHC_BASE 0xB3430000
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//#define UDC_BASE 0xB3440000
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#define SFC_BASE 0xB3440000
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#define GPS_BASE 0xB3480000
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#define ETHC_BASE 0xB34B0000
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#define BCH_BASE 0xB34D0000
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#define MSC0_BASE 0xB3450000
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#define MSC1_BASE 0xB3460000
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#define MSC2_BASE 0xB3470000
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#define OTG_BASE 0xb3500000
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/* APB BUS Devices Base */
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#define CPM_BASE 0xB0000000
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#define INTC_BASE 0xB0001000
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#define TCU_BASE 0xB0002000
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#define WDT_BASE 0xB0002000
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#define OST_BASE 0xB2000000 /* OS Timer */
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#define RTC_BASE 0xB0003000
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#define GPIO_BASE 0xB0010000
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#define AIC_BASE 0xB0020000
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#define DMIC_BASE 0xB0021000
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#define ICDC_BASE 0xB0020000
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#define UART0_BASE 0xB0030000
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#define UART1_BASE 0xB0031000
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#define UART2_BASE 0xB0032000
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#define SCC_BASE 0xB0040000
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#define SSI0_BASE 0xB0043000
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#define SSI1_BASE 0xB0044000
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#define SSI2_BASE 0xB0045000
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#define I2C0_BASE 0xB0050000
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#define I2C1_BASE 0xB0051000
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#define I2C2_BASE 0xB0052000
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#define PS2_BASE 0xB0060000
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#define SADC_BASE 0xB0070000
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#define OWI_BASE 0xB0072000
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#define TSSI_BASE 0xB0073000
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/* NAND CHIP Base Address*/
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#define NEMC_CS1_IOBASE 0Xbb000000
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#define NEMC_CS2_IOBASE 0Xba000000
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#define NEMC_CS3_IOBASE 0Xb9000000
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#define NEMC_CS4_IOBASE 0Xb8000000
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#define NEMC_CS5_IOBASE 0Xb7000000
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#define NEMC_CS6_IOBASE 0Xb6000000
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/*********************************************************************************************************
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** WDT
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*********************************************************************************************************/
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#define WDT_TDR (0x00)
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#define WDT_TCER (0x04)
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#define WDT_TCNT (0x08)
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#define WDT_TCSR (0x0C)
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#define REG_WDT_TDR REG16(WDT_BASE + WDT_TDR)
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#define REG_WDT_TCER REG8(WDT_BASE + WDT_TCER)
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#define REG_WDT_TCNT REG16(WDT_BASE + WDT_TCNT)
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#define REG_WDT_TCSR REG16(WDT_BASE + WDT_TCSR)
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#define WDT_TSCR_WDTSC (1 << 16)
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#define WDT_TCSR_PRESCALE_1 (0 << 3)
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#define WDT_TCSR_PRESCALE_4 (1 << 3)
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#define WDT_TCSR_PRESCALE_16 (2 << 3)
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#define WDT_TCSR_PRESCALE_64 (3 << 3)
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#define WDT_TCSR_PRESCALE_256 (4 << 3)
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#define WDT_TCSR_PRESCALE_1024 (5 << 3)
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#define WDT_TCSR_EXT_EN (1 << 2)
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#define WDT_TCSR_RTC_EN (1 << 1)
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#define WDT_TCSR_PCK_EN (1 << 0)
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#define WDT_TCER_TCEN (1 << 0)
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/* RTC Reg */
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#define RTC_RTCCR (0x00) /* rw, 32, 0x00000081 */
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#define RTC_RTCSR (0x04) /* rw, 32, 0x???????? */
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#define RTC_RTCSAR (0x08) /* rw, 32, 0x???????? */
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#define RTC_RTCGR (0x0c) /* rw, 32, 0x0??????? */
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#define RTC_HCR (0x20) /* rw, 32, 0x00000000 */
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#define RTC_HWFCR (0x24) /* rw, 32, 0x0000???0 */
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#define RTC_HRCR (0x28) /* rw, 32, 0x00000??0 */
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#define RTC_HWCR (0x2c) /* rw, 32, 0x00000008 */
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#define RTC_HWRSR (0x30) /* rw, 32, 0x00000000 */
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#define RTC_HSPR (0x34) /* rw, 32, 0x???????? */
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#define RTC_WENR (0x3c) /* rw, 32, 0x00000000 */
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#define RTC_CKPCR (0x40) /* rw, 32, 0x00000010 */
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#define RTC_OWIPCR (0x44) /* rw, 32, 0x00000010 */
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#define RTC_PWRONCR (0x48) /* rw, 32, 0x???????? */
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#define RTCCR_WRDY BIT(7)
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#define WENR_WEN BIT(31)
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#define RECOVERY_SIGNATURE (0x001a1a)
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#define REBOOT_SIGNATURE (0x003535)
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#define UNMSAK_SIGNATURE (0x7c0000)//do not use these bits
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#include "x1000_cpm.h"
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#include "x1000_intc.h"
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#include "x1000_otg_dwc.h"
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#include "x1000_aic.h"
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#include "x1000_slcdc.h"
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#endif /* _JZ_M150_H_ */
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