2017-05-15 16:12:15 +08:00
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; Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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2015-11-11 06:47:12 +08:00
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;
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2017-05-15 16:12:15 +08:00
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; SPDX-License-Identifier: Apache-2.0
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2015-11-11 06:47:12 +08:00
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;
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2017-05-15 16:12:15 +08:00
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; Licensed under the Apache License, Version 2.0 (the License); you may
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; not use this file except in compliance with the License.
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; You may obtain a copy of the License at
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2015-11-11 06:47:12 +08:00
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;
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2017-05-15 16:12:15 +08:00
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; www.apache.org/licenses/LICENSE-2.0
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2015-11-11 06:47:12 +08:00
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;
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2017-05-15 16:12:15 +08:00
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; Unless required by applicable law or agreed to in writing, software
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; distributed under the License is distributed on an AS IS BASIS, WITHOUT
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; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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; See the License for the specific language governing permissions and
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; limitations under the License.
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2015-11-11 06:47:12 +08:00
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;
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2017-05-15 16:12:15 +08:00
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; NOTICE: This file has been modified by Nordic Semiconductor ASA.
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IF :DEF: __STARTUP_CONFIG
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#include "startup_config.h"
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#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
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#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
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#endif
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ENDIF
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IF :DEF: __STARTUP_CONFIG
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Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
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ELIF :DEF: __STACK_SIZE
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Stack_Size EQU __STACK_SIZE
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ELSE
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Stack_Size EQU 8096
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ENDIF
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IF :DEF: __STARTUP_CONFIG
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Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
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ELSE
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Stack_Align EQU 3
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ENDIF
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AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
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2015-11-11 06:47:12 +08:00
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Stack_Mem SPACE Stack_Size
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__initial_sp
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2017-05-15 16:12:15 +08:00
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IF :DEF: __STARTUP_CONFIG
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Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
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ELIF :DEF: __HEAP_SIZE
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Heap_Size EQU __HEAP_SIZE
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ELSE
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Heap_Size EQU 0
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2015-11-11 06:47:12 +08:00
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ENDIF
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler
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DCD NMI_Handler
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DCD HardFault_Handler
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DCD MemoryManagement_Handler
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DCD BusFault_Handler
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DCD UsageFault_Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler
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DCD DebugMon_Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler
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DCD SysTick_Handler
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; External Interrupts
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DCD POWER_CLOCK_IRQHandler
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DCD RADIO_IRQHandler
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DCD UARTE0_UART0_IRQHandler
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DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
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DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
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DCD NFCT_IRQHandler
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DCD GPIOTE_IRQHandler
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DCD SAADC_IRQHandler
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DCD TIMER0_IRQHandler
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DCD TIMER1_IRQHandler
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DCD TIMER2_IRQHandler
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DCD RTC0_IRQHandler
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DCD TEMP_IRQHandler
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DCD RNG_IRQHandler
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DCD ECB_IRQHandler
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DCD CCM_AAR_IRQHandler
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DCD WDT_IRQHandler
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DCD RTC1_IRQHandler
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DCD QDEC_IRQHandler
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DCD COMP_LPCOMP_IRQHandler
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DCD SWI0_EGU0_IRQHandler
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DCD SWI1_EGU1_IRQHandler
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DCD SWI2_EGU2_IRQHandler
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DCD SWI3_EGU3_IRQHandler
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DCD SWI4_EGU4_IRQHandler
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DCD SWI5_EGU5_IRQHandler
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DCD TIMER3_IRQHandler
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DCD TIMER4_IRQHandler
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DCD PWM0_IRQHandler
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DCD PDM_IRQHandler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD MWU_IRQHandler
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DCD PWM1_IRQHandler
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DCD PWM2_IRQHandler
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DCD SPIM2_SPIS2_SPI2_IRQHandler
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DCD RTC2_IRQHandler
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DCD I2S_IRQHandler
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DCD FPU_IRQHandler
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2015-11-11 06:47:12 +08:00
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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2017-05-15 16:12:15 +08:00
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2015-11-11 06:47:12 +08:00
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemoryManagement_Handler\
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PROC
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EXPORT MemoryManagement_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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2015-11-11 06:47:12 +08:00
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT POWER_CLOCK_IRQHandler [WEAK]
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EXPORT RADIO_IRQHandler [WEAK]
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EXPORT UARTE0_UART0_IRQHandler [WEAK]
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EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK]
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EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK]
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EXPORT NFCT_IRQHandler [WEAK]
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EXPORT GPIOTE_IRQHandler [WEAK]
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EXPORT SAADC_IRQHandler [WEAK]
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EXPORT TIMER0_IRQHandler [WEAK]
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EXPORT TIMER1_IRQHandler [WEAK]
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EXPORT TIMER2_IRQHandler [WEAK]
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EXPORT RTC0_IRQHandler [WEAK]
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EXPORT TEMP_IRQHandler [WEAK]
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EXPORT RNG_IRQHandler [WEAK]
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EXPORT ECB_IRQHandler [WEAK]
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EXPORT CCM_AAR_IRQHandler [WEAK]
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EXPORT WDT_IRQHandler [WEAK]
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EXPORT RTC1_IRQHandler [WEAK]
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EXPORT QDEC_IRQHandler [WEAK]
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EXPORT COMP_LPCOMP_IRQHandler [WEAK]
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EXPORT SWI0_EGU0_IRQHandler [WEAK]
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EXPORT SWI1_EGU1_IRQHandler [WEAK]
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EXPORT SWI2_EGU2_IRQHandler [WEAK]
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EXPORT SWI3_EGU3_IRQHandler [WEAK]
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EXPORT SWI4_EGU4_IRQHandler [WEAK]
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EXPORT SWI5_EGU5_IRQHandler [WEAK]
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EXPORT TIMER3_IRQHandler [WEAK]
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EXPORT TIMER4_IRQHandler [WEAK]
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EXPORT PWM0_IRQHandler [WEAK]
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EXPORT PDM_IRQHandler [WEAK]
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EXPORT MWU_IRQHandler [WEAK]
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EXPORT PWM1_IRQHandler [WEAK]
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EXPORT PWM2_IRQHandler [WEAK]
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EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK]
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EXPORT RTC2_IRQHandler [WEAK]
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EXPORT I2S_IRQHandler [WEAK]
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2017-05-15 16:12:15 +08:00
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EXPORT FPU_IRQHandler [WEAK]
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2015-11-11 06:47:12 +08:00
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POWER_CLOCK_IRQHandler
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RADIO_IRQHandler
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UARTE0_UART0_IRQHandler
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SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
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SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
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NFCT_IRQHandler
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GPIOTE_IRQHandler
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SAADC_IRQHandler
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TIMER0_IRQHandler
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TIMER1_IRQHandler
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TIMER2_IRQHandler
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RTC0_IRQHandler
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TEMP_IRQHandler
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RNG_IRQHandler
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ECB_IRQHandler
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CCM_AAR_IRQHandler
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WDT_IRQHandler
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RTC1_IRQHandler
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QDEC_IRQHandler
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COMP_LPCOMP_IRQHandler
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SWI0_EGU0_IRQHandler
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SWI1_EGU1_IRQHandler
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SWI2_EGU2_IRQHandler
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SWI3_EGU3_IRQHandler
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SWI4_EGU4_IRQHandler
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SWI5_EGU5_IRQHandler
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TIMER3_IRQHandler
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TIMER4_IRQHandler
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PWM0_IRQHandler
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PDM_IRQHandler
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MWU_IRQHandler
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PWM1_IRQHandler
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PWM2_IRQHandler
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SPIM2_SPIS2_SPI2_IRQHandler
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RTC2_IRQHandler
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I2S_IRQHandler
|
2017-05-15 16:12:15 +08:00
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FPU_IRQHandler
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2015-11-11 06:47:12 +08:00
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
|
2017-05-15 16:12:15 +08:00
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2015-11-11 06:47:12 +08:00
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
|
2017-05-15 16:12:15 +08:00
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__user_initial_stackheap PROC
|
2015-11-11 06:47:12 +08:00
|
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LDR R0, = Heap_Mem
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LDR R1, = (Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
|
2017-05-15 16:12:15 +08:00
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ENDP
|
2015-11-11 06:47:12 +08:00
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ALIGN
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ENDIF
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END
|
