510 lines
20 KiB
C
510 lines
20 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FSL_DMA_H_
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#define _FSL_DMA_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup dma
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* @{
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*/
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/*! @file */
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief DMA driver version */
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#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
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/*@}*/
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#define DMA_MAX_TRANSFER_COUNT 0x400
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#if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS
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#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS
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#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS
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#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT)
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#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
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#endif
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/* Channel group consists of 32 channels. channel_group = (channel / 32) */
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#define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U)
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/* Channel index in channel group. channel_index = (channel % 32) */
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#define DMA_CHANNEL_INDEX(channel) (((uint8_t)(channel)) & 0x1F)
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#define DMA_COMMON_REG_GET(base, channel, reg) (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)])
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#define DMA_COMMON_CONST_REG_GET(base, channel, reg) (((volatile const uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)])
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#define DMA_COMMON_REG_SET(base, channel, reg, value) \
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(((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value))
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/*! @brief DMA descriptor structure */
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typedef struct _dma_descriptor
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{
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uint32_t xfercfg; /*!< Transfer configuration */
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void *srcEndAddr; /*!< Last source address of DMA transfer */
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void *dstEndAddr; /*!< Last destination address of DMA transfer */
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void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */
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} dma_descriptor_t;
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/*! @brief DMA transfer configuration */
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typedef struct _dma_xfercfg
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{
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bool valid; /*!< Descriptor is ready to transfer */
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bool reload; /*!< Reload channel configuration register after
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current descriptor is exhausted */
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bool swtrig; /*!< Perform software trigger. Transfer if fired
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when 'valid' is set */
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bool clrtrig; /*!< Clear trigger */
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bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */
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bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */
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uint8_t byteWidth; /*!< Byte width of data to transfer */
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uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */
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uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */
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uint16_t transferCount; /*!< Number of transfers */
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} dma_xfercfg_t;
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/*! @brief DMA channel priority */
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typedef enum _dma_priority
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{
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kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */
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kDMA_ChannelPriority1, /*!< Channel priority 1 */
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kDMA_ChannelPriority2, /*!< Channel priority 2 */
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kDMA_ChannelPriority3, /*!< Channel priority 3 */
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kDMA_ChannelPriority4, /*!< Channel priority 4 */
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kDMA_ChannelPriority5, /*!< Channel priority 5 */
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kDMA_ChannelPriority6, /*!< Channel priority 6 */
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kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */
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} dma_priority_t;
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/*! @brief DMA interrupt flags */
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typedef enum _dma_int
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{
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kDMA_IntA, /*!< DMA interrupt flag A */
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kDMA_IntB, /*!< DMA interrupt flag B */
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kDMA_IntError, /*!< DMA interrupt flag error */
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} dma_irq_t;
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/*! @brief DMA trigger type*/
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typedef enum _dma_trigger_type
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{
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kDMA_NoTrigger = 0, /*!< Trigger is disabled */
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kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */
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kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) |
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DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */
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kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */
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kDMA_RisingEdgeTrigger =
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DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */
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} dma_trigger_type_t;
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/*! @brief DMA trigger burst */
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typedef enum _dma_trigger_burst
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{
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kDMA_SingleTransfer = 0, /*!< Single transfer */
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kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */
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kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */
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kDMA_EdgeBurstTransfer2 =
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DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */
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kDMA_EdgeBurstTransfer4 =
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DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */
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kDMA_EdgeBurstTransfer8 =
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DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */
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kDMA_EdgeBurstTransfer16 =
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DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */
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kDMA_EdgeBurstTransfer32 =
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DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */
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kDMA_EdgeBurstTransfer64 =
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DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */
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kDMA_EdgeBurstTransfer128 =
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DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */
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kDMA_EdgeBurstTransfer256 =
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DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */
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kDMA_EdgeBurstTransfer512 =
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DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */
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kDMA_EdgeBurstTransfer1024 =
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DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */
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} dma_trigger_burst_t;
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/*! @brief DMA burst wrapping */
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typedef enum _dma_burst_wrap
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{
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kDMA_NoWrap = 0, /*!< Wrapping is disabled */
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kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */
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kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */
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kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) |
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DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */
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} dma_burst_wrap_t;
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/*! @brief DMA transfer type */
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typedef enum _dma_transfer_type
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{
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kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */
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kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */
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kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/
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kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */
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} dma_transfer_type_t;
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/*! @brief DMA channel trigger */
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typedef struct _dma_channel_trigger
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{
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dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */
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dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */
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dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */
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} dma_channel_trigger_t;
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/*! @brief DMA transfer status */
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enum _dma_transfer_status
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{
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kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the
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transfer request. */
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};
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/*! @brief DMA transfer configuration */
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typedef struct _dma_transfer_config
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{
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uint8_t *srcAddr; /*!< Source data address */
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uint8_t *dstAddr; /*!< Destination data address */
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uint8_t *nextDesc; /*!< Chain custom descriptor */
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dma_xfercfg_t xfercfg; /*!< Transfer options */
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bool isPeriph; /*!< DMA transfer is driven by peripheral */
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} dma_transfer_config_t;
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/*! @brief Callback for DMA */
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struct _dma_handle;
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/*! @brief Define Callback function for DMA. */
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typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode);
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/*! @brief DMA transfer handle structure */
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typedef struct _dma_handle
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{
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dma_callback callback; /*!< Callback function. Invoked when transfer
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of descriptor with interrupt flag finishes */
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void *userData; /*!< Callback function parameter */
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DMA_Type *base; /*!< DMA peripheral base address */
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uint8_t channel; /*!< DMA channel number */
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} dma_handle_t;
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/*******************************************************************************
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* APIs
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus */
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/*!
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* @name DMA initialization and De-initialization
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* @{
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*/
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/*!
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* @brief Initializes DMA peripheral.
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*
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* This function enable the DMA clock, set descriptor table and
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* enable DMA peripheral.
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*
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* @param base DMA peripheral base address.
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*/
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void DMA_Init(DMA_Type *base);
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/*!
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* @brief Deinitializes DMA peripheral.
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*
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* This function gates the DMA clock.
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*
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* @param base DMA peripheral base address.
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*/
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void DMA_Deinit(DMA_Type *base);
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/* @} */
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/*!
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* @name DMA Channel Operation
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* @{
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*/
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/*!
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* @brief Return whether DMA channel is processing transfer
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*
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* @param base DMA peripheral base address.
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* @param channel DMA channel number.
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* @return True for active state, false otherwise.
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*/
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static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel)
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{
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assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
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return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false;
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}
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/*!
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* @brief Enables the interrupt source for the DMA transfer.
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*
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* @param base DMA peripheral base address.
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* @param channel DMA channel number.
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*/
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static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel)
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{
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assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
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DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1U << DMA_CHANNEL_INDEX(channel);
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}
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/*!
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* @brief Disables the interrupt source for the DMA transfer.
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*
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* @param base DMA peripheral base address.
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* @param channel DMA channel number.
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*/
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static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel)
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{
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assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
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DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1U << DMA_CHANNEL_INDEX(channel);
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}
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/*!
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* @brief Enable DMA channel.
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*
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* @param base DMA peripheral base address.
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* @param channel DMA channel number.
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*/
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static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel)
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{
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assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
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DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1U << DMA_CHANNEL_INDEX(channel);
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}
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/*!
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* @brief Disable DMA channel.
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*
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* @param base DMA peripheral base address.
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* @param channel DMA channel number.
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*/
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static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel)
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{
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assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
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DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1U << DMA_CHANNEL_INDEX(channel);
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}
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/*!
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* @brief Set PERIPHREQEN of channel configuration register.
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*
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* @param base DMA peripheral base address.
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* @param channel DMA channel number.
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*/
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static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel)
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{
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assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
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base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
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}
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/*!
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* @brief Get PERIPHREQEN value of channel configuration register.
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*
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* @param base DMA peripheral base address.
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* @param channel DMA channel number.
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|
* @return True for enabled PeriphRq, false for disabled.
|
||
|
|
*/
|
||
|
|
static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel)
|
||
|
|
{
|
||
|
|
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
|
||
|
|
base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Set trigger settings of DMA channel.
|
||
|
|
*
|
||
|
|
* @param base DMA peripheral base address.
|
||
|
|
* @param channel DMA channel number.
|
||
|
|
* @param trigger trigger configuration.
|
||
|
|
*/
|
||
|
|
void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Gets the remaining bytes of the current DMA descriptor transfer.
|
||
|
|
*
|
||
|
|
* @param base DMA peripheral base address.
|
||
|
|
* @param channel DMA channel number.
|
||
|
|
* @return The number of bytes which have not been transferred yet.
|
||
|
|
*/
|
||
|
|
uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Set priority of channel configuration register.
|
||
|
|
*
|
||
|
|
* @param base DMA peripheral base address.
|
||
|
|
* @param channel DMA channel number.
|
||
|
|
* @param priority Channel priority value.
|
||
|
|
*/
|
||
|
|
static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority)
|
||
|
|
{
|
||
|
|
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
|
||
|
|
base->CHANNEL[channel].CFG =
|
||
|
|
(base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Get priority of channel configuration register.
|
||
|
|
*
|
||
|
|
* @param base DMA peripheral base address.
|
||
|
|
* @param channel DMA channel number.
|
||
|
|
* @return Channel priority value.
|
||
|
|
*/
|
||
|
|
static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel)
|
||
|
|
{
|
||
|
|
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
|
||
|
|
return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >>
|
||
|
|
DMA_CHANNEL_CFG_CHPRIORITY_SHIFT);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Create application specific DMA descriptor
|
||
|
|
* to be used in a chain in transfer
|
||
|
|
*
|
||
|
|
* @param desc DMA descriptor address.
|
||
|
|
* @param xfercfg Transfer configuration for DMA descriptor.
|
||
|
|
* @param srcAddr Address of last item to transmit
|
||
|
|
* @param dstAddr Address of last item to receive.
|
||
|
|
* @param nextDesc Address of next descriptor in chain.
|
||
|
|
*/
|
||
|
|
void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc);
|
||
|
|
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @name DMA Transactional Operation
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Abort running transfer by handle.
|
||
|
|
*
|
||
|
|
* This function aborts DMA transfer specified by handle.
|
||
|
|
*
|
||
|
|
* @param handle DMA handle pointer.
|
||
|
|
*/
|
||
|
|
void DMA_AbortTransfer(dma_handle_t *handle);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Creates the DMA handle.
|
||
|
|
*
|
||
|
|
* This function is called if using transaction API for DMA. This function
|
||
|
|
* initializes the internal state of DMA handle.
|
||
|
|
*
|
||
|
|
* @param handle DMA handle pointer. The DMA handle stores callback function and
|
||
|
|
* parameters.
|
||
|
|
* @param base DMA peripheral base address.
|
||
|
|
* @param channel DMA channel number.
|
||
|
|
*/
|
||
|
|
void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Installs a callback function for the DMA transfer.
|
||
|
|
*
|
||
|
|
* This callback is called in DMA IRQ handler. Use the callback to do something after
|
||
|
|
* the current major loop transfer completes.
|
||
|
|
*
|
||
|
|
* @param handle DMA handle pointer.
|
||
|
|
* @param callback DMA callback function pointer.
|
||
|
|
* @param userData Parameter for callback function.
|
||
|
|
*/
|
||
|
|
void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Prepares the DMA transfer structure.
|
||
|
|
*
|
||
|
|
* This function prepares the transfer configuration structure according to the user input.
|
||
|
|
*
|
||
|
|
* @param config The user configuration structure of type dma_transfer_t.
|
||
|
|
* @param srcAddr DMA transfer source address.
|
||
|
|
* @param dstAddr DMA transfer destination address.
|
||
|
|
* @param byteWidth DMA transfer destination address width(bytes).
|
||
|
|
* @param transferBytes DMA transfer bytes to be transferred.
|
||
|
|
* @param type DMA transfer type.
|
||
|
|
* @param nextDesc Chain custom descriptor to transfer.
|
||
|
|
* @note The data address and the data width must be consistent. For example, if the SRC
|
||
|
|
* is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in
|
||
|
|
* source address error(SAE).
|
||
|
|
*/
|
||
|
|
void DMA_PrepareTransfer(dma_transfer_config_t *config,
|
||
|
|
void *srcAddr,
|
||
|
|
void *dstAddr,
|
||
|
|
uint32_t byteWidth,
|
||
|
|
uint32_t transferBytes,
|
||
|
|
dma_transfer_type_t type,
|
||
|
|
void *nextDesc);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Submits the DMA transfer request.
|
||
|
|
*
|
||
|
|
* This function submits the DMA transfer request according to the transfer configuration structure.
|
||
|
|
* If the user submits the transfer request repeatedly, this function packs an unprocessed request as
|
||
|
|
* a TCD and enables scatter/gather feature to process it in the next time.
|
||
|
|
*
|
||
|
|
* @param handle DMA handle pointer.
|
||
|
|
* @param config Pointer to DMA transfer configuration structure.
|
||
|
|
* @retval kStatus_DMA_Success It means submit transfer request succeed.
|
||
|
|
* @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
|
||
|
|
* @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later.
|
||
|
|
*/
|
||
|
|
status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief DMA start transfer.
|
||
|
|
*
|
||
|
|
* This function enables the channel request. User can call this function after submitting the transfer request
|
||
|
|
* or before submitting the transfer request.
|
||
|
|
*
|
||
|
|
* @param handle DMA handle pointer.
|
||
|
|
*/
|
||
|
|
void DMA_StartTransfer(dma_handle_t *handle);
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief DMA IRQ handler for descriptor transfer complete.
|
||
|
|
*
|
||
|
|
* This function clears the channel major interrupt flag and call
|
||
|
|
* the callback function if it is not NULL.
|
||
|
|
*/
|
||
|
|
void DMA_HandleIRQ(void);
|
||
|
|
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
#if defined(__cplusplus)
|
||
|
|
}
|
||
|
|
#endif /* __cplusplus */
|
||
|
|
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
#endif /*_FSL_DMA_H_*/
|