2023-08-15 18:41:20 +08:00
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/*
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2024-05-31 19:46:47 +08:00
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* Copyright (c) 2023-2024 HPMicro
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2023-08-15 18:41:20 +08:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Change Logs:
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* Date Author Notes
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* 2023-04-07 HPMicro the first version
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2024-05-31 19:46:47 +08:00
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* 2023-05-31 HPMicro add MCAN4-MCAN7 support
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2023-08-15 18:41:20 +08:00
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <rthw.h>
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#include "board.h"
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#include "hpm_mcan_drv.h"
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2024-05-31 19:46:47 +08:00
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2023-08-15 18:41:20 +08:00
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#define CAN_SEND_WAIT_MS_MAX (1000U) /* CAN maximum wait time for transmission */
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#define CAN_SENDBOX_NUM (1U) /* CAN Hardware Transmission buffer number */
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#define CAN_STD_FILTER_NUM_MAX (128U) /* std Filter number */
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#define CAN_EXT_FILTER_NUM_MAX (64U) /* ext Filter number */
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#ifdef RT_USING_CAN
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typedef struct _hpm_can_struct
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{
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MCAN_Type *can_base; /**< CAN Base address */
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const char *name; /**< CAN device name */
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int32_t irq_num; /**< CAN IRQ index */
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uint32_t fifo_index; /**< FIFO index, it is a fake value to satisfy the driver framework */
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mcan_config_t can_config; /**< CAN configuration for IP */
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struct rt_can_device can_dev; /**< CAN device configuration in rt-thread */
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uint32_t irq_txrx_err_enable_mask; /**< CAN TX and RX IRQ Enable Mask */
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uint32_t std_filter_num; /**< std Filter number */
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mcan_filter_elem_t std_can_filters[CAN_STD_FILTER_NUM_MAX];
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uint32_t ext_filter_num; /**< ext Filter number */
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mcan_filter_elem_t ext_can_filters[CAN_EXT_FILTER_NUM_MAX];
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} hpm_can_t;
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static const mcan_filter_elem_t k_default_std_id_filter = {
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/* Use classic filter */
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.filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER,
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/* Store message into RXFIFO0 if matching */
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.filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH,
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/* For Standard Identify only */
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.can_id_type = MCAN_CAN_ID_TYPE_STANDARD,
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/* Sync Message, only evaluated when "CCCR.UTSU" is set */
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.sync_message = 0U,
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/* Don't care if mask is set to all 1s */
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.filter_id = 0U,
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/* Accept all messages */
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.filter_mask = 0x7FFU,
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};
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static const mcan_filter_elem_t k_default_ext_id_filter = {
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/* Use classic filter */
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.filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER,
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/* Store message into RXFIFO0 if matching */
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.filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH,
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/* For Standard Identify only */
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.can_id_type = MCAN_CAN_ID_TYPE_EXTENDED,
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/* Sync Message, only evaluated when "CCCR.UTSU" is set */
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.sync_message = 0,
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/* Don't care if mask is set to all 1s */
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.filter_id = 0,
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/* Accept all messages */
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.filter_mask = 0x1FFFFFFFUL,
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};
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/**
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* @brief Configure CAN controller
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* @param [in/out] can CAN device pointer
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* @param [in] cfg CAN configuration pointer
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* @retval RT_EOK for valid configuration
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* @retval -RT_ERROR for invalid configuration
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*/
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static rt_err_t hpm_mcan_configure(struct rt_can_device *can, struct can_configure *cfg);
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/**
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* @brief Control/Get CAN state
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* including:interrupt, mode, priority, baudrate, filter, status
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* @param [in/out] can CAN device pointer
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* @param [in] cmd Control command
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* @param [in/out] arg Argument pointer
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* @retval RT_EOK for valid control command and arg
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* @retval -RT_ERROR for invalid control command or arg
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*/
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static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg);
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/**
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* @brief Send out CAN message
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* @param [in] can CAN device pointer
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* @param [in] buf CAN message buffer
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* @param [in] boxno Mailbox number, it is not used in this porting
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* @retval RT_EOK No error
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* @retval -RT_ETIMEOUT timeout happened
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* @retval -RT_EFULL Transmission buffer is full
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*/
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static int hpm_mcan_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno);
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/**
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* @brief Receive message from CAN
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* @param [in] can CAN device pointer
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* @param [out] buf CAN receive buffer
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* @param [in] boxno Mailbox Number, it is not used in this porting
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* @retval RT_EOK no error
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* @retval -RT_ERROR Error happened during reading receive FIFO
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* @retval -RT_EMPTY no data in receive FIFO
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*/
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static int hpm_mcan_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno);
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/**
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* @brief Common Interrupt Service routine
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* @param [in] hpm_can HPM CAN pointer
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*/
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static void hpm_mcan_isr(hpm_can_t *hpm_can);
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/**
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* @brief Decode data bytes from DLC
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* @param [in] dlc Data Length Code
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* @return decoded data bytes
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*/
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static uint8_t can_get_data_bytes_from_dlc(uint32_t dlc);
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#if defined(HPM_MCAN0_BASE) && defined(BSP_USING_MCAN0)
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static hpm_can_t dev_can0 =
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{
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.can_base = HPM_MCAN0,
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.name = "can0",
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2024-05-31 19:46:47 +08:00
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.irq_num = IRQn_MCAN0,
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2023-08-15 18:41:20 +08:00
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.fifo_index = 0,
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};
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void can0_isr(void)
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{
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hpm_mcan_isr(&dev_can0);
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}
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2024-05-31 19:46:47 +08:00
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SDK_DECLARE_EXT_ISR_M(IRQn_MCAN0, can0_isr);
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2023-08-15 18:41:20 +08:00
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#endif
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#if defined(HPM_MCAN1_BASE) && defined(BSP_USING_MCAN1)
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static hpm_can_t dev_can1 =
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{
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.can_base = HPM_MCAN1,
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.name = "can1",
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2024-05-31 19:46:47 +08:00
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.irq_num = IRQn_MCAN1,
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2023-08-15 18:41:20 +08:00
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.fifo_index = 1,
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};
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void can1_isr(void)
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{
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hpm_mcan_isr(&dev_can1);
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}
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2024-05-31 19:46:47 +08:00
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SDK_DECLARE_EXT_ISR_M(IRQn_MCAN1, can1_isr);
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2023-08-15 18:41:20 +08:00
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#endif
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#if defined(HPM_MCAN2_BASE) && defined(BSP_USING_MCAN2)
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static hpm_can_t dev_can2 =
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{
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.can_base = HPM_MCAN2,
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.name = "can2",
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2024-05-31 19:46:47 +08:00
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.irq_num = IRQn_MCAN2,
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2023-08-15 18:41:20 +08:00
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.fifo_index = 2,
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};
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void can2_isr(void)
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{
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hpm_mcan_isr(&dev_can2);
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}
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2024-05-31 19:46:47 +08:00
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SDK_DECLARE_EXT_ISR_M(IRQn_MCAN2, can2_isr);
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2023-08-15 18:41:20 +08:00
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#endif
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#if defined(HPM_MCAN3_BASE) && defined(BSP_USING_MCAN3)
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static hpm_can_t dev_can3 =
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{
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.can_base = HPM_MCAN3,
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.name = "can3",
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2024-05-31 19:46:47 +08:00
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.irq_num = IRQn_MCAN3,
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2023-08-15 18:41:20 +08:00
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.fifo_index = 3,
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};
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void can3_isr(void)
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{
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hpm_mcan_isr(&dev_can3);
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}
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2024-05-31 19:46:47 +08:00
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SDK_DECLARE_EXT_ISR_M(IRQn_MCAN3, can3_isr);
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#endif
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#if defined(HPM_MCAN4_BASE) && defined(BSP_USING_MCAN4)
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static hpm_can_t dev_can4 =
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{
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.can_base = HPM_MCAN4,
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.name = "can4",
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.irq_num = IRQn_MCAN4,
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.fifo_index = 4,
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};
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void can4_isr(void)
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{
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hpm_mcan_isr(&dev_can4);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_MCAN4, can4_isr);
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#endif
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#if defined(HPM_MCAN5_BASE) && defined(BSP_USING_MCAN5)
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static hpm_can_t dev_can5 =
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{
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.can_base = HPM_MCAN5,
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.name = "can5",
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.irq_num = IRQn_MCAN5,
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.fifo_index = 5,
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};
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void can5_isr(void)
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{
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hpm_mcan_isr(&dev_can5);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_MCAN5, can5_isr);
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#endif
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#if defined(HPM_MCAN6_BASE) && defined(BSP_USING_MCAN6)
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static hpm_can_t dev_can6 =
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{
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.can_base = HPM_MCAN6,
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.name = "can6",
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.irq_num = IRQn_MCAN6,
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.fifo_index = 6,
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};
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void can6_isr(void)
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{
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hpm_mcan_isr(&dev_can6);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_MCAN6, can6_isr);
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#endif
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#if defined(HPM_MCAN7_BASE) && defined(BSP_USING_MCAN7)
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static hpm_can_t dev_can7 =
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{
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.can_base = HPM_MCAN7,
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.name = "can7",
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.irq_num = IRQn_MCAN7,
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.fifo_index = 7,
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};
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void can7_isr(void)
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{
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hpm_mcan_isr(&dev_can7);
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}
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SDK_DECLARE_EXT_ISR_M(IRQn_MCAN7, can7_isr);
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2023-08-15 18:41:20 +08:00
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#endif
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static hpm_can_t *hpm_cans[] = {
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#if defined(HPM_MCAN0_BASE) && defined(BSP_USING_MCAN0)
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&dev_can0,
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#endif
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#if defined(HPM_MCAN1_BASE) && defined(BSP_USING_MCAN1)
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&dev_can1,
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#endif
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#if defined(HPM_MCAN2_BASE) && defined(BSP_USING_MCAN2)
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&dev_can2,
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#endif
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#if defined(HPM_MCAN3_BASE) && defined(BSP_USING_MCAN3)
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&dev_can3,
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2024-05-31 19:46:47 +08:00
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#endif
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#if defined(HPM_MCAN4_BASE) && defined(BSP_USING_MCAN4)
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&dev_can4,
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#endif
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#if defined(HPM_MCAN5_BASE) && defined(BSP_USING_MCAN5)
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&dev_can5,
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#endif
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#if defined(HPM_MCAN6_BASE) && defined(BSP_USING_MCAN6)
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&dev_can6,
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#endif
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#if defined(HPM_MCAN7_BASE) && defined(BSP_USING_MCAN7)
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&dev_can7,
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2023-08-15 18:41:20 +08:00
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#endif
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};
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static const struct rt_can_ops hpm_can_ops = {
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.configure = hpm_mcan_configure,
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.control = hpm_mcan_control,
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.sendmsg = hpm_mcan_sendmsg,
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.recvmsg = hpm_mcan_recvmsg,
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};
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static void hpm_mcan_isr(hpm_can_t *hpm_can)
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{
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uint8_t error_flags = mcan_get_last_error_code(hpm_can->can_base);
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uint32_t flags = mcan_get_interrupt_flags(hpm_can->can_base);
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mcan_error_count_t err_cnt;
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/* Transmit completed */
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if ((flags & (MCAN_EVENT_TRANSMIT)) != 0U) {
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rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_TX_DONE | (0UL << 8));
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}
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/* Data available in FIFO */
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if ((flags & MCAN_EVENT_RECEIVE) != 0)
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{
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rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RX_IND | (hpm_can->fifo_index << 8));
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}
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/* RX FIFO overflow */
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if ((flags & MCAN_INT_RXFIFO0_FULL) != 0U)
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{
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rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RXOF_IND | (hpm_can->fifo_index << 8));
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}
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if ((flags & MCAN_INT_RXFIFO1_FULL) != 0U)
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{
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rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RXOF_IND | (hpm_can->fifo_index << 8));
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}
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/* Error happened on CAN Bus */
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if (((flags & MCAN_EVENT_ERROR) != 0U) || (error_flags != 0U))
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{
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mcan_get_error_counter(hpm_can->can_base, &err_cnt);
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switch(error_flags)
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{
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case 3:
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hpm_can->can_dev.status.ackerrcnt++;
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break;
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case 4:
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hpm_can->can_dev.status.biterrcnt++;
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break;
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case 6:
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hpm_can->can_dev.status.crcerrcnt++;
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break;
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case 2:
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hpm_can->can_dev.status.formaterrcnt++;
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break;
|
|
|
|
case 1:
|
|
|
|
hpm_can->can_dev.status.bitpaderrcnt++;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
hpm_can->can_dev.status.rcverrcnt = err_cnt.receive_error_count;
|
|
|
|
hpm_can->can_dev.status.snderrcnt = err_cnt.transmit_error_count;
|
|
|
|
hpm_can->can_dev.status.lasterrtype = mcan_get_last_error_code(hpm_can->can_base);
|
|
|
|
hpm_can->can_dev.status.errcode = 0;
|
|
|
|
if ((error_flags & MCAN_INT_WARNING_STATUS) != 0U)
|
|
|
|
{
|
|
|
|
hpm_can->can_dev.status.errcode |= ERRWARNING;
|
|
|
|
}
|
|
|
|
if ((error_flags & MCAN_INT_ERROR_PASSIVE) != 0U)
|
|
|
|
{
|
|
|
|
hpm_can->can_dev.status.errcode |= ERRPASSIVE;
|
|
|
|
}
|
|
|
|
if (mcan_is_in_busoff_state(hpm_can->can_base))
|
|
|
|
{
|
|
|
|
hpm_can->can_dev.status.errcode |= BUSOFF;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
mcan_clear_interrupt_flags(hpm_can->can_base, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static rt_err_t hpm_mcan_configure(struct rt_can_device *can, struct can_configure *cfg)
|
|
|
|
{
|
|
|
|
RT_ASSERT(can);
|
|
|
|
RT_ASSERT(cfg);
|
|
|
|
|
|
|
|
hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data;
|
|
|
|
RT_ASSERT(drv_can);
|
|
|
|
|
|
|
|
#ifdef RT_CAN_USING_CANFD
|
|
|
|
drv_can->can_config.enable_canfd = (cfg->enable_canfd != 0) ? true : false;
|
|
|
|
if (cfg->use_bit_timing != 0U)
|
|
|
|
{
|
|
|
|
drv_can->can_config.use_lowlevel_timing_setting = true;
|
|
|
|
drv_can->can_config.can_timing.prescaler = cfg->can_timing.prescaler;
|
|
|
|
drv_can->can_config.can_timing.num_seg1 = cfg->can_timing.num_seg1;
|
|
|
|
drv_can->can_config.can_timing.num_seg2 = cfg->can_timing.num_seg2;
|
|
|
|
drv_can->can_config.can_timing.num_sjw = cfg->can_timing.num_sjw;
|
|
|
|
|
|
|
|
drv_can->can_config.canfd_timing.prescaler = cfg->canfd_timing.prescaler;
|
|
|
|
drv_can->can_config.canfd_timing.num_seg1 = cfg->canfd_timing.num_seg1;
|
|
|
|
drv_can->can_config.canfd_timing.num_seg2 = cfg->canfd_timing.num_seg2;
|
|
|
|
drv_can->can_config.canfd_timing.num_sjw = cfg->canfd_timing.num_sjw;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
#endif
|
|
|
|
{
|
|
|
|
drv_can->can_config.use_lowlevel_timing_setting = false;
|
|
|
|
drv_can->can_config.baudrate = cfg->baud_rate;
|
|
|
|
#ifdef RT_CAN_USING_CANFD
|
|
|
|
drv_can->can_config.baudrate_fd = cfg->baud_rate_fd;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
switch (cfg->mode)
|
|
|
|
{
|
|
|
|
case RT_CAN_MODE_NORMAL:
|
|
|
|
drv_can->can_config.mode = mcan_mode_normal;
|
|
|
|
break;
|
|
|
|
case RT_CAN_MODE_LISTEN:
|
|
|
|
drv_can->can_config.mode = mcan_mode_listen_only;
|
|
|
|
break;
|
|
|
|
case RT_CAN_MODE_LOOPBACK:
|
|
|
|
drv_can->can_config.mode = mcan_mode_loopback_internal;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -RT_ERROR;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
init_can_pins(drv_can->can_base);
|
|
|
|
uint32_t can_clk = board_init_can_clock(drv_can->can_base);
|
|
|
|
|
|
|
|
drv_can->can_config.all_filters_config.std_id_filter_list.filter_elem_list = &drv_can->std_can_filters[0];
|
|
|
|
drv_can->can_config.all_filters_config.std_id_filter_list.mcan_filter_elem_count = drv_can->std_filter_num;
|
|
|
|
drv_can->can_config.all_filters_config.ext_id_filter_list.filter_elem_list = &drv_can->ext_can_filters[0];
|
|
|
|
drv_can->can_config.all_filters_config.ext_id_filter_list.mcan_filter_elem_count = drv_can->ext_filter_num;
|
|
|
|
drv_can->can_config.all_filters_config.ext_id_mask = (1UL << 30) - 1UL;
|
2024-05-31 19:46:47 +08:00
|
|
|
drv_can->can_config.txbuf_trans_interrupt_mask = ~0UL;
|
2023-08-15 18:41:20 +08:00
|
|
|
|
|
|
|
hpm_stat_t status = mcan_init(drv_can->can_base, &drv_can->can_config, can_clk);
|
|
|
|
if (status != status_success)
|
|
|
|
{
|
|
|
|
return -RT_ERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg)
|
|
|
|
{
|
|
|
|
RT_ASSERT(can);
|
|
|
|
|
|
|
|
hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data;
|
|
|
|
RT_ASSERT(drv_can);
|
|
|
|
|
|
|
|
uint32_t arg_val;
|
|
|
|
rt_err_t err = RT_EOK;
|
|
|
|
|
|
|
|
uint32_t temp;
|
2024-05-31 19:46:47 +08:00
|
|
|
uint32_t irq_txrx_mask;
|
2023-08-15 18:41:20 +08:00
|
|
|
|
|
|
|
switch (cmd)
|
|
|
|
{
|
|
|
|
case RT_DEVICE_CTRL_CLR_INT:
|
|
|
|
arg_val = (uint32_t) arg;
|
|
|
|
intc_m_disable_irq(drv_can->irq_num);
|
|
|
|
if (arg_val == RT_DEVICE_FLAG_INT_RX)
|
|
|
|
{
|
2024-05-31 19:46:47 +08:00
|
|
|
irq_txrx_mask = MCAN_EVENT_RECEIVE;
|
2023-08-15 18:41:20 +08:00
|
|
|
drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask;
|
2024-05-31 19:46:47 +08:00
|
|
|
drv_can->can_config.interrupt_mask &= ~irq_txrx_mask;
|
2023-08-15 18:41:20 +08:00
|
|
|
mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask);
|
|
|
|
}
|
|
|
|
else if (arg_val == RT_DEVICE_FLAG_INT_TX)
|
|
|
|
{
|
2024-05-31 19:46:47 +08:00
|
|
|
irq_txrx_mask = MCAN_EVENT_TRANSMIT;
|
2023-08-15 18:41:20 +08:00
|
|
|
drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask;
|
2024-05-31 19:46:47 +08:00
|
|
|
drv_can->can_config.interrupt_mask &= ~irq_txrx_mask;
|
2023-08-15 18:41:20 +08:00
|
|
|
mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask);
|
|
|
|
mcan_disable_txbuf_interrupt(drv_can->can_base, ~0UL);
|
|
|
|
} else if (arg_val == RT_DEVICE_CAN_INT_ERR) {
|
2024-05-31 19:46:47 +08:00
|
|
|
irq_txrx_mask = MCAN_EVENT_ERROR;
|
2023-08-15 18:41:20 +08:00
|
|
|
drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask;
|
2024-05-31 19:46:47 +08:00
|
|
|
drv_can->can_config.interrupt_mask &= ~irq_txrx_mask;
|
2023-08-15 18:41:20 +08:00
|
|
|
mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask);
|
|
|
|
} else {
|
|
|
|
err = -RT_ERROR;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case RT_DEVICE_CTRL_SET_INT:
|
|
|
|
arg_val = (uint32_t) arg;
|
|
|
|
if (arg_val == RT_DEVICE_FLAG_INT_RX)
|
|
|
|
{
|
2024-05-31 19:46:47 +08:00
|
|
|
irq_txrx_mask = MCAN_EVENT_RECEIVE;
|
2023-08-15 18:41:20 +08:00
|
|
|
drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask;
|
2024-05-31 19:46:47 +08:00
|
|
|
drv_can->can_config.interrupt_mask |= irq_txrx_mask;
|
2023-08-15 18:41:20 +08:00
|
|
|
mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask);
|
|
|
|
intc_m_enable_irq_with_priority(drv_can->irq_num, 1);
|
|
|
|
}
|
|
|
|
else if (arg_val == RT_DEVICE_FLAG_INT_TX)
|
|
|
|
{
|
2024-05-31 19:46:47 +08:00
|
|
|
irq_txrx_mask = MCAN_EVENT_TRANSMIT;
|
2023-08-15 18:41:20 +08:00
|
|
|
drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask;
|
2024-05-31 19:46:47 +08:00
|
|
|
drv_can->can_config.interrupt_mask |= irq_txrx_mask;
|
2023-08-15 18:41:20 +08:00
|
|
|
mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask);
|
|
|
|
mcan_enable_txbuf_interrupt(drv_can->can_base, ~0UL);
|
|
|
|
intc_m_enable_irq_with_priority(drv_can->irq_num, 1);
|
|
|
|
}
|
|
|
|
else if (arg_val == RT_DEVICE_CAN_INT_ERR)
|
|
|
|
{
|
2024-05-31 19:46:47 +08:00
|
|
|
irq_txrx_mask = MCAN_EVENT_ERROR;
|
2023-08-15 18:41:20 +08:00
|
|
|
drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask;
|
2024-05-31 19:46:47 +08:00
|
|
|
drv_can->can_config.interrupt_mask |= irq_txrx_mask;
|
2023-08-15 18:41:20 +08:00
|
|
|
mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask);
|
|
|
|
intc_m_enable_irq_with_priority(drv_can->irq_num, 1);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
err = -RT_ERROR;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case RT_CAN_CMD_SET_FILTER:
|
|
|
|
{
|
|
|
|
/* Convert the RT-Thread Filter format to the filter format supported by HPM CAN */
|
|
|
|
struct rt_can_filter_config *filter = (struct rt_can_filter_config*)arg;
|
|
|
|
drv_can->std_filter_num = 0;
|
|
|
|
drv_can->ext_filter_num = 0;
|
|
|
|
if (filter != NULL)
|
|
|
|
{
|
|
|
|
for (uint32_t i = 0; i < filter->count; i++)
|
|
|
|
{
|
|
|
|
if (filter->items[i].ide != 0)
|
|
|
|
{
|
|
|
|
drv_can->ext_can_filters[drv_can->ext_filter_num].filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER;
|
|
|
|
drv_can->ext_can_filters[drv_can->ext_filter_num].filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH;
|
|
|
|
drv_can->ext_can_filters[drv_can->ext_filter_num].can_id_type = MCAN_CAN_ID_TYPE_EXTENDED;
|
|
|
|
drv_can->ext_can_filters[drv_can->ext_filter_num].filter_id = filter->items[i].id;
|
|
|
|
drv_can->ext_can_filters[drv_can->ext_filter_num].filter_mask = filter->items[i].mask;
|
|
|
|
drv_can->ext_filter_num++;
|
|
|
|
RT_ASSERT(drv_can->ext_filter_num <= CAN_EXT_FILTER_NUM_MAX);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
drv_can->std_can_filters[drv_can->std_filter_num].filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER;
|
|
|
|
drv_can->std_can_filters[drv_can->std_filter_num].filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH;
|
|
|
|
drv_can->std_can_filters[drv_can->std_filter_num].can_id_type = MCAN_CAN_ID_TYPE_STANDARD;
|
|
|
|
drv_can->std_can_filters[drv_can->std_filter_num].filter_id = filter->items[i].id;
|
|
|
|
drv_can->std_can_filters[drv_can->std_filter_num].filter_mask = filter->items[i].mask;
|
|
|
|
drv_can->std_filter_num++;
|
|
|
|
RT_ASSERT(drv_can->std_filter_num <= CAN_STD_FILTER_NUM_MAX);
|
|
|
|
|
|
|
|
}
|
|
|
|
if (filter->items[i].rtr != 0)
|
|
|
|
{
|
|
|
|
if (drv_can->ext_filter_num)
|
|
|
|
{
|
|
|
|
drv_can->can_config.all_filters_config.global_filter_config.reject_remote_ext_frame = false;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
drv_can->can_config.all_filters_config.global_filter_config.reject_remote_ext_frame = true;
|
|
|
|
}
|
|
|
|
if (drv_can->std_filter_num)
|
|
|
|
{
|
|
|
|
drv_can->can_config.all_filters_config.global_filter_config.reject_remote_std_frame = false;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
drv_can->can_config.all_filters_config.global_filter_config.reject_remote_std_frame = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (filter->actived != 0U)
|
|
|
|
{
|
|
|
|
drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_std_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_REJECT;
|
|
|
|
drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_ext_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_REJECT;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_std_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0;
|
|
|
|
drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_ext_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
drv_can->can_config.all_filters_config.global_filter_config.reject_remote_ext_frame = false;
|
|
|
|
drv_can->can_config.all_filters_config.global_filter_config.reject_remote_std_frame = false;
|
|
|
|
drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_std_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0;
|
|
|
|
drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_ext_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0;
|
|
|
|
drv_can->can_config.all_filters_config.ext_id_mask = 0x1FFFFFFFUL;
|
|
|
|
drv_can->can_config.all_filters_config.std_id_filter_list.filter_elem_list = &k_default_std_id_filter;
|
|
|
|
drv_can->can_config.all_filters_config.std_id_filter_list.mcan_filter_elem_count = 1;
|
|
|
|
drv_can->can_config.all_filters_config.ext_id_filter_list.filter_elem_list = &k_default_ext_id_filter;
|
|
|
|
drv_can->can_config.all_filters_config.ext_id_filter_list.mcan_filter_elem_count = 1;
|
|
|
|
}
|
|
|
|
err = hpm_mcan_configure(can, &drv_can->can_dev.config);
|
2024-05-31 19:46:47 +08:00
|
|
|
#ifdef RT_CAN_USING_HDR
|
|
|
|
if (filter == RT_NULL) {
|
|
|
|
/*if use RT_CAN_USING_HDR, but if want to receive everything without filtering, use default filter, need to return NO-RT-OK status*/
|
|
|
|
err = -RT_ETRAP;
|
|
|
|
}
|
|
|
|
#endif
|
2023-08-15 18:41:20 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case RT_CAN_CMD_SET_MODE:
|
|
|
|
arg_val = (uint32_t) arg;
|
|
|
|
if ((arg_val != RT_CAN_MODE_NORMAL) && (arg_val != RT_CAN_MODE_LISTEN) && (arg_val != RT_CAN_MODE_LOOPBACK))
|
|
|
|
{
|
|
|
|
err = -RT_ERROR;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (arg_val != drv_can->can_dev.config.mode)
|
|
|
|
{
|
|
|
|
drv_can->can_dev.config.mode = arg_val;
|
|
|
|
err = hpm_mcan_configure(can, &drv_can->can_dev.config);
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
case RT_CAN_CMD_SET_BAUD:
|
|
|
|
arg_val = (uint32_t) arg;
|
|
|
|
if (arg_val != drv_can->can_dev.config.baud_rate)
|
|
|
|
{
|
|
|
|
drv_can->can_dev.config.baud_rate = arg_val;
|
|
|
|
}
|
|
|
|
err = hpm_mcan_configure(can, &drv_can->can_dev.config);
|
|
|
|
break;
|
|
|
|
#ifdef RT_CAN_USING_CANFD
|
|
|
|
case RT_CAN_CMD_SET_CANFD:
|
|
|
|
arg_val = (uint32_t) arg;
|
|
|
|
if (arg_val != drv_can->can_dev.config.enable_canfd)
|
|
|
|
{
|
|
|
|
drv_can->can_dev.config.enable_canfd = arg_val;
|
|
|
|
err = hpm_mcan_configure(can, &drv_can->can_dev.config);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case RT_CAN_CMD_SET_BAUD_FD:
|
|
|
|
arg_val = (uint32_t) arg;
|
|
|
|
if (arg_val != drv_can->can_dev.config.baud_rate_fd)
|
|
|
|
{
|
|
|
|
drv_can->can_dev.config.baud_rate_fd = arg_val;
|
|
|
|
err = hpm_mcan_configure(can, &drv_can->can_dev.config);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case RT_CAN_CMD_SET_BITTIMING:
|
|
|
|
{
|
|
|
|
struct rt_can_bit_timing_config *timing_configs = (struct rt_can_bit_timing_config*)arg;
|
|
|
|
if ((timing_configs == RT_NULL) || (timing_configs->count < 1) || (timing_configs->count > 2))
|
|
|
|
{
|
|
|
|
return -RT_ERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (timing_configs->count != 0U)
|
|
|
|
{
|
|
|
|
drv_can->can_dev.config.can_timing = timing_configs->items[0];
|
|
|
|
}
|
|
|
|
if (timing_configs->count == 2)
|
|
|
|
{
|
|
|
|
drv_can->can_dev.config.canfd_timing = timing_configs->items[1];
|
|
|
|
}
|
|
|
|
err = hpm_mcan_configure(can, &drv_can->can_dev.config);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
case RT_CAN_CMD_SET_PRIV:
|
|
|
|
arg_val = (uint32_t)arg;
|
|
|
|
if ((arg_val != RT_CAN_MODE_PRIV) && (arg_val != RT_CAN_MODE_NOPRIV))
|
|
|
|
{
|
|
|
|
return -RT_ERROR;
|
|
|
|
}
|
|
|
|
if (arg_val != drv_can->can_dev.config.privmode)
|
|
|
|
{
|
|
|
|
drv_can->can_dev.config.privmode = arg_val;
|
|
|
|
err = hpm_mcan_configure(can, &drv_can->can_dev.config);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case RT_CAN_CMD_GET_STATUS:
|
|
|
|
mcan_error_count_t err_cnt;
|
|
|
|
mcan_get_error_counter(drv_can->can_base, &err_cnt);
|
|
|
|
drv_can->can_dev.status.rcverrcnt = err_cnt.receive_error_count;
|
|
|
|
drv_can->can_dev.status.snderrcnt = err_cnt.transmit_error_count;
|
|
|
|
drv_can->can_dev.status.lasterrtype = mcan_get_last_error_code(drv_can->can_base);
|
|
|
|
temp = mcan_get_interrupt_flags(drv_can->can_base);
|
|
|
|
drv_can->can_dev.status.errcode = 0;
|
|
|
|
if ((temp & MCAN_INT_WARNING_STATUS) != 0U)
|
|
|
|
{
|
|
|
|
drv_can->can_dev.status.errcode |= ERRWARNING;
|
|
|
|
}
|
|
|
|
if ((temp & MCAN_INT_ERROR_PASSIVE) != 0U)
|
|
|
|
{
|
|
|
|
drv_can->can_dev.status.errcode |= ERRPASSIVE;
|
|
|
|
}
|
|
|
|
if (mcan_is_in_busoff_state(drv_can->can_base))
|
|
|
|
{
|
|
|
|
drv_can->can_dev.status.errcode |= BUSOFF;
|
|
|
|
}
|
|
|
|
rt_memcpy(arg, &drv_can->can_dev.status, sizeof(drv_can->can_dev.status));
|
|
|
|
break;
|
|
|
|
}
|
2024-05-31 19:46:47 +08:00
|
|
|
return err;
|
2023-08-15 18:41:20 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int hpm_mcan_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno)
|
|
|
|
{
|
|
|
|
RT_ASSERT(can);
|
|
|
|
|
|
|
|
hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data;
|
|
|
|
RT_ASSERT(drv_can);
|
|
|
|
|
|
|
|
struct rt_can_msg *can_msg = (struct rt_can_msg *) buf;
|
|
|
|
|
|
|
|
mcan_tx_frame_t tx_frame = {0};
|
|
|
|
memset(&tx_frame, 0, sizeof(tx_frame));
|
|
|
|
if (can_msg->ide == RT_CAN_STDID)
|
|
|
|
{
|
|
|
|
tx_frame.use_ext_id = 0;
|
|
|
|
tx_frame.std_id = can_msg->id;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
tx_frame.use_ext_id = 1;
|
|
|
|
tx_frame.ext_id = can_msg->id;
|
|
|
|
}
|
|
|
|
if (can_msg->rtr == RT_CAN_DTR)
|
|
|
|
{
|
|
|
|
tx_frame.rtr = false;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
tx_frame.rtr = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef RT_CAN_USING_CANFD
|
2024-05-31 19:46:47 +08:00
|
|
|
tx_frame.bitrate_switch = can_msg->brs;
|
2023-08-15 18:41:20 +08:00
|
|
|
if (can_msg->fd_frame != 0)
|
|
|
|
{
|
|
|
|
tx_frame.canfd_frame = 1;
|
|
|
|
RT_ASSERT(can_msg->len <= 15);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
#endif
|
|
|
|
{
|
|
|
|
RT_ASSERT(can_msg->len <= 8);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t msg_len = mcan_get_message_size_from_dlc(can_msg->len);
|
|
|
|
for (uint32_t i = 0; i < msg_len; i++)
|
|
|
|
{
|
|
|
|
tx_frame.data_8[i] = can_msg->data[i];
|
|
|
|
}
|
|
|
|
tx_frame.dlc = can_msg->len;
|
|
|
|
|
|
|
|
uint32_t delay_cnt = 0;
|
|
|
|
while (mcan_is_txfifo_full(drv_can->can_base))
|
|
|
|
{
|
|
|
|
rt_thread_mdelay(1);
|
|
|
|
delay_cnt++;
|
|
|
|
if (delay_cnt >= CAN_SEND_WAIT_MS_MAX)
|
|
|
|
{
|
|
|
|
return -RT_ETIMEOUT;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
hpm_stat_t status = mcan_transmit_via_txbuf_nonblocking(drv_can->can_base, 0, &tx_frame);
|
|
|
|
if (status != status_success)
|
|
|
|
{
|
|
|
|
return -RT_EFULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hpm_mcan_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno)
|
|
|
|
{
|
|
|
|
RT_ASSERT(can);
|
|
|
|
|
|
|
|
hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data;
|
|
|
|
RT_ASSERT(drv_can);
|
|
|
|
|
|
|
|
rt_can_msg_t can_msg = (rt_can_msg_t)buf;
|
|
|
|
mcan_rx_message_t rx_buf;
|
|
|
|
hpm_stat_t status = mcan_read_rxfifo(drv_can->can_base, 0, &rx_buf);
|
|
|
|
if (status == status_success)
|
|
|
|
{
|
|
|
|
if (rx_buf.use_ext_id)
|
|
|
|
{
|
|
|
|
can_msg->ide = RT_CAN_EXTID;
|
|
|
|
can_msg->id = rx_buf.ext_id;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
can_msg->ide = RT_CAN_STDID;
|
|
|
|
can_msg->id = rx_buf.std_id;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
if (rx_buf.rtr != 0) {
|
|
|
|
can_msg->rtr = RT_CAN_RTR;
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
can_msg->rtr = RT_CAN_DTR;
|
|
|
|
}
|
2024-05-31 19:46:47 +08:00
|
|
|
#ifdef RT_CAN_USING_CANFD
|
|
|
|
can_msg->fd_frame = rx_buf.canfd_frame;
|
|
|
|
can_msg->brs = rx_buf.bitrate_switch;
|
|
|
|
#endif
|
2023-08-15 18:41:20 +08:00
|
|
|
can_msg->len = rx_buf.dlc;
|
|
|
|
uint32_t msg_len = mcan_get_message_size_from_dlc(can_msg->len);
|
|
|
|
for(uint32_t i = 0; i < msg_len; i++) {
|
|
|
|
can_msg->data[i] = rx_buf.data_8[i];
|
|
|
|
}
|
2024-05-31 19:46:47 +08:00
|
|
|
#ifdef RT_CAN_USING_HDR
|
|
|
|
/* Hardware filter messages are valid */
|
|
|
|
can_msg->hdr_index = boxno;
|
|
|
|
can->hdr[can_msg->hdr_index].connected = 1;
|
|
|
|
#endif
|
2023-08-15 18:41:20 +08:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
return -RT_EEMPTY;
|
|
|
|
}
|
|
|
|
|
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
|
|
|
|
int rt_hw_mcan_init(void)
|
|
|
|
{
|
|
|
|
struct can_configure config = CANDEFAULTCONFIG;
|
|
|
|
config.privmode = RT_CAN_MODE_NOPRIV;
|
|
|
|
config.sndboxnumber = CAN_SENDBOX_NUM;
|
|
|
|
config.ticks = 50;
|
2024-05-31 19:46:47 +08:00
|
|
|
#ifdef RT_CAN_USING_HDR
|
|
|
|
config.maxhdr = 32;
|
|
|
|
#endif
|
2023-08-15 18:41:20 +08:00
|
|
|
for (uint32_t i = 0; i < ARRAY_SIZE(hpm_cans); i++)
|
|
|
|
{
|
|
|
|
hpm_cans[i]->can_dev.config = config;
|
|
|
|
hpm_cans[i]->ext_filter_num = 0;
|
|
|
|
hpm_cans[i]->std_filter_num = 0;
|
|
|
|
mcan_get_default_config(hpm_cans[i]->can_base, &hpm_cans[i]->can_config);
|
|
|
|
rt_hw_can_register(&hpm_cans[i]->can_dev, hpm_cans[i]->name, &hpm_can_ops, hpm_cans[i]);
|
|
|
|
}
|
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
|
|
|
|
INIT_BOARD_EXPORT(rt_hw_mcan_init);
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|