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rt-thread/libcpu/arm/cortex-r4/context_ccs.asm

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add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
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;/*
rm48x50: utilize CPS instruction and remove some useless code
2013-05-26 16:55:39 +08:00
; * File : context_ccs.asm
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
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; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2006, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2009-01-20 Bernard first version
; * 2011-07-22 Bernard added thumb mode porting
; * 2013-05-24 Grissiom port to CCS
rm48x50: utilize CPS instruction and remove some useless code
2013-05-26 16:55:39 +08:00
; * 2013-05-26 Grissiom optimize for ARMv7
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
; */
.text
.arm
.ref rt_thread_switch_interrupt_flag
.ref rt_interrupt_from_thread
.ref rt_interrupt_to_thread
.ref rt_interrupt_enter
.ref rt_interrupt_leave
.ref rt_hw_trap_irq
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
.def rt_hw_interrupt_disable
cortex-r4: wrap asm functions with .asmfunc/.endasmfunc
2013-05-31 22:43:53 +08:00
.asmfunc
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
rt_hw_interrupt_disable
MRS r0, cpsr
rm48x50: utilize CPS instruction and remove some useless code
2013-05-26 16:55:39 +08:00
CPSID IF
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
BX lr
cortex-r4: wrap asm functions with .asmfunc/.endasmfunc
2013-05-31 22:43:53 +08:00
.endasmfunc
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
.def rt_hw_interrupt_enable
cortex-r4: wrap asm functions with .asmfunc/.endasmfunc
2013-05-31 22:43:53 +08:00
.asmfunc
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
rt_hw_interrupt_enable
MSR cpsr_c, r0
BX lr
cortex-r4: wrap asm functions with .asmfunc/.endasmfunc
2013-05-31 22:43:53 +08:00
.endasmfunc
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
; * r0 --> from
; * r1 --> to
; */
.def rt_hw_context_switch
cortex-r4: wrap asm functions with .asmfunc/.endasmfunc
2013-05-31 22:43:53 +08:00
.asmfunc
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
rt_hw_context_switch
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
STMDB sp!, {lr} ; push pc (lr should be pushed in place of PC)
STMDB sp!, {r0-r12, lr} ; push lr & register file
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
MRS r4, cpsr
TST lr, #0x01
rm48x50: optimize a BEQ Use condition flag in the ORR. This could eliminate a BEQ.
2013-05-26 23:37:56 +08:00
ORRNE r4, r4, #0x20 ; it's thumb code
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
STMDB sp!, {r4} ; push cpsr
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
.if (__TI_VFP_SUPPORT__)
VMRS r4, fpexc
TST r4, #0x40000000
BEQ __no_vfp_frame1
VSTMDB sp!, {d0-d15}
VMRS r5, fpscr
; TODO: add support for Common VFPv3.
; Save registers like FPINST, FPINST2
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
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STMDB sp!, {r5}
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
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__no_vfp_frame1
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
STMDB sp!, {r4}
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
.endif
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
STR sp, [r0] ; store sp in preempted tasks TCB
LDR sp, [r1] ; get new task stack pointer
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
.if (__TI_VFP_SUPPORT__)
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r0} ; get fpexc
rm48x50: VFP lazy stacking You need to turn on RT_VFP_LAZY_STACKING in rtconfig.h. By default, RTT will turn on VFP for all threads and stack all the VFP registers. When doing lazy stacking, VFP will only be turned on for the thread who issued VFP instructions. Currently, if a thread turned on VFP, it cannot be turned off. RTT will never know what time the thread doesn't need VFP any more. The thread might could turn off the VFP for it self in proper time.
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VMSR fpexc, r0 ; restore fpexc
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
TST r0, #0x40000000
BEQ __no_vfp_frame2
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r1} ; get fpscr
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
VMSR fpscr, r1
VLDMIA sp!, {d0-d15}
__no_vfp_frame2
.endif
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r4} ; pop new task cpsr to spsr
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
MSR spsr_cxsf, r4
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
cortex-r4: wrap asm functions with .asmfunc/.endasmfunc
2013-05-31 22:43:53 +08:00
.endasmfunc
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; */
.def rt_hw_context_switch_to
cortex-r4: wrap asm functions with .asmfunc/.endasmfunc
2013-05-31 22:43:53 +08:00
.asmfunc
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
rt_hw_context_switch_to
LDR sp, [r0] ; get new task stack pointer
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
.if (__TI_VFP_SUPPORT__)
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r0} ; get fpexc
rm48x50: VFP lazy stacking You need to turn on RT_VFP_LAZY_STACKING in rtconfig.h. By default, RTT will turn on VFP for all threads and stack all the VFP registers. When doing lazy stacking, VFP will only be turned on for the thread who issued VFP instructions. Currently, if a thread turned on VFP, it cannot be turned off. RTT will never know what time the thread doesn't need VFP any more. The thread might could turn off the VFP for it self in proper time.
2013-05-31 20:25:44 +08:00
VMSR fpexc, r0
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
TST r0, #0x40000000
BEQ __no_vfp_frame_to
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r1} ; get fpscr
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
VMSR fpscr, r1
VLDMIA sp!, {d0-d15}
__no_vfp_frame_to
.endif
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r4} ; pop new task cpsr to spsr
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
MSR spsr_cxsf, r4
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
cortex-r4: wrap asm functions with .asmfunc/.endasmfunc
2013-05-31 22:43:53 +08:00
.endasmfunc
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
;/*
; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
; */
.def rt_hw_context_switch_interrupt
cortex-r4: wrap asm functions with .asmfunc/.endasmfunc
2013-05-31 22:43:53 +08:00
.asmfunc
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
rt_hw_context_switch_interrupt
LDR r2, pintflag
LDR r3, [r2]
CMP r3, #1
BEQ _reswitch
MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1
STR r3, [r2]
LDR r2, pfromthread ; set rt_interrupt_from_thread
STR r0, [r2]
_reswitch
LDR r2, ptothread ; set rt_interrupt_to_thread
STR r1, [r2]
BX lr
cortex-r4: wrap asm functions with .asmfunc/.endasmfunc
2013-05-31 22:43:53 +08:00
.endasmfunc
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
.def IRQ_Handler
IRQ_Handler
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
STMDB sp!, {r0-r12,lr}
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
.if (__TI_VFP_SUPPORT__)
VMRS r0, fpexc
TST r0, #0x40000000
BEQ __no_vfp_frame_str_irq
VSTMDB sp!, {d0-d15}
VMRS r1, fpscr
; TODO: add support for Common VFPv3.
; Save registers like FPINST, FPINST2
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
STMDB sp!, {r1}
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
__no_vfp_frame_str_irq
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
STMDB sp!, {r0}
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
.endif
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
BL rt_interrupt_enter
BL rt_hw_trap_irq
BL rt_interrupt_leave
; if rt_thread_switch_interrupt_flag set, jump to
; rt_hw_context_switch_interrupt_do and don't return
LDR r0, pintflag
LDR r1, [r0]
CMP r1, #1
BEQ rt_hw_context_switch_interrupt_do
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
.if (__TI_VFP_SUPPORT__)
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r0} ; get fpexc
rm48x50: VFP lazy stacking You need to turn on RT_VFP_LAZY_STACKING in rtconfig.h. By default, RTT will turn on VFP for all threads and stack all the VFP registers. When doing lazy stacking, VFP will only be turned on for the thread who issued VFP instructions. Currently, if a thread turned on VFP, it cannot be turned off. RTT will never know what time the thread doesn't need VFP any more. The thread might could turn off the VFP for it self in proper time.
2013-05-31 20:25:44 +08:00
VMSR fpexc, r0
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
TST r0, #0x40000000
BEQ __no_vfp_frame_ldr_irq
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r1} ; get fpscr
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
VMSR fpscr, r1
VLDMIA sp!, {d0-d15}
__no_vfp_frame_ldr_irq
.endif
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r0-r12,lr}
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
SUBS pc, lr, #4
; /*
; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
; */
.def rt_hw_context_switch_interrupt_do
rt_hw_context_switch_interrupt_do
MOV r1, #0 ; clear flag
STR r1, [r0]
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
.if (__TI_VFP_SUPPORT__)
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r0} ; get fpexc
rm48x50: VFP lazy stacking You need to turn on RT_VFP_LAZY_STACKING in rtconfig.h. By default, RTT will turn on VFP for all threads and stack all the VFP registers. When doing lazy stacking, VFP will only be turned on for the thread who issued VFP instructions. Currently, if a thread turned on VFP, it cannot be turned off. RTT will never know what time the thread doesn't need VFP any more. The thread might could turn off the VFP for it self in proper time.
2013-05-31 20:25:44 +08:00
VMSR fpexc, r0
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
TST r0, #0x40000000
BEQ __no_vfp_frame_do1
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r1} ; get fpscr
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
VMSR fpscr, r1
VLDMIA sp!, {d0-d15}
__no_vfp_frame_do1
.endif
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r0-r12,lr} ; reload saved registers
STMDB sp, {r0-r3} ; save r0-r3. We will restore r0-r3 in the SVC
rm48x50: optimize context_switch_interrupt_do Substitude STMFD, MOV, ADD with STMFD, SUB. It reduce one instruction. Tested on board and it works like a charm.
2013-05-26 17:10:49 +08:00
; mode so there is no need to update SP.
SUB r1, sp, #16 ; save the right SP value in r1, so we could restore r0-r3.
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
SUB r2, lr, #4 ; save old task's pc to r2
MRS r3, spsr ; get cpsr of interrupt thread
; switch to SVC mode and no interrupt
rm48x50: utilize CPS instruction and remove some useless code
2013-05-26 16:55:39 +08:00
CPSID IF, #0x13
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
STMDB sp!, {r2} ; push old task's pc
STMDB sp!, {r4-r12,lr} ; push old task's lr,r12-r4
LDMIA r1!, {r4-r7} ; restore r0-r3 of the interrupted thread
STMDB sp!, {r4-r7} ; push old task's r3-r0. We don't need to push/pop them to
rm48x50: optimize context_switch_interrupt_to by reuse registers When saving thread registers in context_switch_interrupt_to, we don't change them, just move them. So there is no need to always r0-r3 from stack to the real r0-r3. So just use the intermediate registers and eliminate 2 MOV.
2013-05-26 22:37:49 +08:00
; r0-r3 because we just want to transfer the data and don't
; use them here.
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
STMDB sp!, {r3} ; push old task's cpsr
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
.if (__TI_VFP_SUPPORT__)
VMRS r0, fpexc
TST r0, #0x40000000
BEQ __no_vfp_frame_do2
rm48x50: VFP lazy stacking You need to turn on RT_VFP_LAZY_STACKING in rtconfig.h. By default, RTT will turn on VFP for all threads and stack all the VFP registers. When doing lazy stacking, VFP will only be turned on for the thread who issued VFP instructions. Currently, if a thread turned on VFP, it cannot be turned off. RTT will never know what time the thread doesn't need VFP any more. The thread might could turn off the VFP for it self in proper time.
2013-05-31 20:25:44 +08:00
VSTMDB sp!, {d0-d15}
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
VMRS r1, fpscr
; TODO: add support for Common VFPv3.
; Save registers like FPINST, FPINST2
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
STMDB sp!, {r1}
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
__no_vfp_frame_do2
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
STMDB sp!, {r0}
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
.endif
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
LDR r4, pfromthread
LDR r5, [r4]
STR sp, [r5] ; store sp in preempted tasks's TCB
LDR r6, ptothread
LDR r6, [r6]
LDR sp, [r6] ; get new task's stack pointer
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
.if (__TI_VFP_SUPPORT__)
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r0} ; get fpexc
rm48x50: VFP lazy stacking You need to turn on RT_VFP_LAZY_STACKING in rtconfig.h. By default, RTT will turn on VFP for all threads and stack all the VFP registers. When doing lazy stacking, VFP will only be turned on for the thread who issued VFP instructions. Currently, if a thread turned on VFP, it cannot be turned off. RTT will never know what time the thread doesn't need VFP any more. The thread might could turn off the VFP for it self in proper time.
2013-05-31 20:25:44 +08:00
VMSR fpexc, r0
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
TST r0, #0x40000000
BEQ __no_vfp_frame_do3
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r1} ; get fpscr
rm48x50: turn on VFP support This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
VMSR fpscr, r1
VLDMIA sp!, {d0-d15}
__no_vfp_frame_do3
.endif
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r4} ; pop new task's cpsr to spsr
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
MSR spsr_cxsf, r4
rm48x50: change STMFD/LDMFD to STMDB/LDMIA VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
LDMIA sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr
add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-05-24 10:04:51 +08:00
pintflag .word rt_thread_switch_interrupt_flag
pfromthread .word rt_interrupt_from_thread
ptothread .word rt_interrupt_to_thread