203 lines
7.9 KiB
C
203 lines
7.9 KiB
C
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/*
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* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-04-28 CDT first version
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*/
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#ifndef __DMA_CONFIG_H__
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#define __DMA_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* DMA1 ch0 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_RX_DMA_INSTANCE CM_DMA1
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#define SPI1_RX_DMA_CHANNEL DMA_CH0
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#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0
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#define SPI1_RX_DMA_IRQn INT038_IRQn
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#define SPI1_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
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#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
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#endif
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/* DMA1 ch1 */
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_TX_DMA_INSTANCE CM_DMA1
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#define SPI1_TX_DMA_CHANNEL DMA_CH1
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#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1
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#define SPI1_TX_DMA_IRQn INT039_IRQn
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#define SPI1_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
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#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
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#endif
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/* DMA1 ch2 */
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#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
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#define SPI2_RX_DMA_INSTANCE CM_DMA1
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#define SPI2_RX_DMA_CHANNEL DMA_CH2
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#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2
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#define SPI2_RX_DMA_IRQn INT040_IRQn
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#define SPI2_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
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#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
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#endif
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/* DMA1 ch3 */
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#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
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#define SPI2_TX_DMA_INSTANCE CM_DMA1
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#define SPI2_TX_DMA_CHANNEL DMA_CH3
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#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3
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#define SPI2_TX_DMA_IRQn INT041_IRQn
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#define SPI2_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
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#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3
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#endif
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/* DMA1 ch4 */
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#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
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#define SPI3_RX_DMA_INSTANCE CM_DMA1
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#define SPI3_RX_DMA_CHANNEL DMA_CH4
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#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4
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#define SPI3_RX_DMA_IRQn INT042_IRQn
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#define SPI3_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
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#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4
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#endif
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/* DMA1 ch5 */
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#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
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#define SPI3_TX_DMA_INSTANCE CM_DMA1
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#define SPI3_TX_DMA_CHANNEL DMA_CH5
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#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5
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#define SPI3_TX_DMA_IRQn INT043_IRQn
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#define SPI3_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
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#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5
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#endif
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/* DMA1 ch6 */
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#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
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#define SPI4_RX_DMA_INSTANCE CM_DMA1
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#define SPI4_RX_DMA_CHANNEL DMA_CH6
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#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6
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#define SPI4_RX_DMA_IRQn INT018_IRQn
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#define SPI4_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
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#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6
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#endif
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/* DMA1 ch7 */
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#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
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#define SPI4_TX_DMA_INSTANCE CM_DMA1
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#define SPI4_TX_DMA_CHANNEL DMA_CH7
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#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
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#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7
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#define SPI4_TX_DMA_IRQn INT019_IRQn
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#define SPI4_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
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#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7
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#endif
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/* DMA2 ch0 */
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#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
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#define UART1_RX_DMA_INSTANCE CM_DMA2
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#define UART1_RX_DMA_CHANNEL DMA_CH0
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#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
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#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0
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#define UART1_RX_DMA_IRQn INT044_IRQn
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#define UART1_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
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#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0
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#endif
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/* DMA2 ch1 */
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#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
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#define UART1_TX_DMA_INSTANCE CM_DMA2
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#define UART1_TX_DMA_CHANNEL DMA_CH1
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#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
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#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1
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#define UART1_TX_DMA_IRQn INT045_IRQn
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#define UART1_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
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#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1
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#endif
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/* DMA2 ch2 */
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#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
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#define UART2_RX_DMA_INSTANCE CM_DMA2
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#define UART2_RX_DMA_CHANNEL DMA_CH2
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#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
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#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2
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#define UART2_RX_DMA_IRQn INT046_IRQn
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#define UART2_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
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#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2
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#endif
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/* DMA2 ch3 */
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#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
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#define UART2_TX_DMA_INSTANCE CM_DMA2
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#define UART2_TX_DMA_CHANNEL DMA_CH3
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#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
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#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3
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#define UART2_TX_DMA_IRQn INT047_IRQn
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#define UART2_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
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#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3
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#endif
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/* DMA2 ch4 */
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#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
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#define UART6_RX_DMA_INSTANCE CM_DMA2
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#define UART6_RX_DMA_CHANNEL DMA_CH4
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#define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
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#define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4
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#define UART6_RX_DMA_IRQn INT048_IRQn
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#define UART6_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
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#define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4
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#endif
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/* DMA2 ch5 */
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#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
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#define UART6_TX_DMA_INSTANCE CM_DMA2
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#define UART6_TX_DMA_CHANNEL DMA_CH5
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#define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
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#define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5
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#define UART6_TX_DMA_IRQn INT049_IRQn
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#define UART6_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
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#define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5
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#endif
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/* DMA2 ch6 */
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#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE)
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#define UART7_RX_DMA_INSTANCE CM_DMA2
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#define UART7_RX_DMA_CHANNEL DMA_CH6
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#define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
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#define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6
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#define UART7_RX_DMA_IRQn INT020_IRQn
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#define UART7_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
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#define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6
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#endif
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/* DMA2 ch7 */
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#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE)
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#define UART7_TX_DMA_INSTANCE CM_DMA2
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#define UART7_TX_DMA_CHANNEL DMA_CH7
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#define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
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#define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7
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#define UART7_TX_DMA_IRQn INT021_IRQn
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#define UART7_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
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#define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DMA_CONFIG_H__ */
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