2021-12-26 23:03:27 +08:00
|
|
|
/*
|
|
|
|
|
* Copyright (c) 2006-2021, RT-Thread Development Team
|
|
|
|
|
*
|
|
|
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
|
|
|
*
|
|
|
|
|
* Change Logs:
|
|
|
|
|
* Date Author Notes
|
|
|
|
|
* 2021-12-05 supperthomas first version
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifndef __BOARD_H__
|
|
|
|
|
#define __BOARD_H__
|
|
|
|
|
|
|
|
|
|
#include <stm32l4xx.h>
|
|
|
|
|
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
extern "C" {
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef BSP_USING_GPIO
|
|
|
|
|
#include "drv_gpio.h"
|
|
|
|
|
|
|
|
|
|
/* Board Pin definitions */
|
|
|
|
|
|
|
|
|
|
#endif /* BSP_USING_GPIO */
|
|
|
|
|
|
|
|
|
|
/* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/
|
|
|
|
|
#define STM32_SRAM_SIZE 64
|
|
|
|
|
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
|
|
|
|
|
|
|
|
|
|
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
|
|
|
|
|
#define STM32_FLASH_SIZE (256 * 1024)
|
|
|
|
|
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
|
|
|
|
|
|
2021-12-30 03:14:07 +08:00
|
|
|
#if defined(__ARMCC_VERSION)
|
2021-12-26 23:03:27 +08:00
|
|
|
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
|
|
|
|
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
|
|
|
|
|
#elif __ICCARM__
|
|
|
|
|
#pragma section="CSTACK"
|
|
|
|
|
#define HEAP_BEGIN (__segment_end("CSTACK"))
|
|
|
|
|
#else
|
|
|
|
|
extern int __bss_end;
|
|
|
|
|
#define HEAP_BEGIN ((void *)&__bss_end)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#define HEAP_END STM32_SRAM_END
|
|
|
|
|
|
|
|
|
|
void SystemClock_Config(void);
|
|
|
|
|
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
