104 lines
4.0 KiB
C
104 lines
4.0 KiB
C
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/******************************************************************************************************************************************
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* <EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: SWM320_sdram.c
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: SWM320<EFBFBD><EFBFBD>Ƭ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>SDRAM<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>֧<EFBFBD><EFBFBD>: http://www.synwit.com.cn/e/tool/gbook/?bid=1
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* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:
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* <EFBFBD>汾<EFBFBD><EFBFBD><EFBFBD><EFBFBD>: V1.1.0 2017<EFBFBD><EFBFBD>10<EFBFBD><EFBFBD>25<EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¼:
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*
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*
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*******************************************************************************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
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* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
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* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
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* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
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* -ECTION WITH THEIR PRODUCTS.
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*
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* COPYRIGHT 2012 Synwit Technology
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*******************************************************************************************************************************************/
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#include "SWM320.h"
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#include "SWM320_sdram.h"
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/******************************************************************************************************************************************
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: SDRAM_Init()
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: SDRAM<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: SDRAM_InitStructure * initStruct <EFBFBD><EFBFBD><EFBFBD><EFBFBD> SDRAM <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>趨ֵ<EFBFBD>Ľṹ<EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
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* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
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******************************************************************************************************************************************/
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void SDRAM_Init(SDRAM_InitStructure * initStruct)
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{
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uint32_t row_n;
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SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos);
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SYS->CLKDIV &= ~SYS_CLKDIV_SDRAM_Msk;
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SYS->CLKDIV |= (1 << SYS_CLKDIV_SDRAM_Pos); //2<><32>Ƶ
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SDRAMC->CR0 = (2 << SDRAMC_CR0_BURSTLEN_Pos) | //2 Burst LengthΪ4
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(initStruct->CASLatency << SDRAMC_CR0_CASDELAY_Pos);
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SDRAMC->CR1 = (initStruct->CellSize << SDRAMC_CR1_CELLSIZE_Pos) |
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(initStruct->CellWidth << SDRAMC_CR1_CELL32BIT_Pos) |
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(initStruct->CellBank << SDRAMC_CR1_BANK_Pos) |
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(0 << SDRAMC_CR1_32BIT_Pos) |
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(initStruct->TimeTMRD << SDRAMC_CR1_TMRD_Pos) |
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(initStruct->TimeTRRD << SDRAMC_CR1_TRRD_Pos) |
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(initStruct->TimeTRAS << SDRAMC_CR1_TRAS_Pos) |
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(initStruct->TimeTRC << SDRAMC_CR1_TRC_Pos) |
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(initStruct->TimeTRCD << SDRAMC_CR1_TRCD_Pos) |
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(initStruct->TimeTRP << SDRAMC_CR1_TRP_Pos);
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SDRAMC->LATCH = 0x02;
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switch(initStruct->CellSize)
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{
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case SDRAM_CELLSIZE_16Mb: row_n = 11; break;
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case SDRAM_CELLSIZE_64Mb: row_n = 12; break;
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case SDRAM_CELLSIZE_128Mb: row_n = 12; break;
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case SDRAM_CELLSIZE_256Mb: row_n = 13; break;
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default: row_n = 13; break;
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}
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SDRAMC->REFRESH = (1 << SDRAMC_REFRESH_EN_Pos) |
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(((SystemCoreClock/2)/1000*64 / (1 << row_n)) << SDRAMC_REFRESH_RATE_Pos);
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while(SDRAMC->REFDONE == 0);
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}
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/******************************************************************************************************************************************
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: SDRAM_Enable()
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: SDRAMʹ<EFBFBD>ܣ<EFBFBD>ʹ<EFBFBD>ܺ<EFBFBD><EFBFBD>ɶ<EFBFBD>дSDRAM
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* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
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* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
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******************************************************************************************************************************************/
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void SDRAM_Enable(void)
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{
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uint32_t i;
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SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos);
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SDRAMC->REFRESH |= (1 << SDRAMC_REFRESH_EN_Pos);
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for(i = 0; i < 100; i++) __NOP();
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}
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/******************************************************************************************************************************************
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: SDRAM_Disable()
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>: SDRAM<EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܺ<EFBFBD>SDRAM<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ˢ<EFBFBD>£<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɶ<EFBFBD>д
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* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
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* ע<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
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******************************************************************************************************************************************/
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void SDRAM_Disable(void)
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{
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uint32_t i;
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SYS->CLKEN |= (1 << SYS_CLKEN_SDRAM_Pos);
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SDRAMC->REFRESH &= ~(1 << SDRAMC_REFRESH_EN_Pos);
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for(i = 0; i < 100; i++) __NOP();
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}
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