2021-09-23 23:20:16 +08:00
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/*
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2023-02-11 08:21:14 +08:00
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* Copyright (c) 2006-2023, RT-Thread Development Team
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2021-09-23 23:20:16 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-09-23 charlown first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <board.h>
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#ifdef BSP_USING_PWM
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#define LOG_TAG "drv.pwm"
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#include <drv_log.h>
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#ifndef ITEM_NUM
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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#endif
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#define MAX_COUNTER 65535
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#define MIN_COUNTER 2
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#define MIN_PULSE 2
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struct rtdevice_pwm_device
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{
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struct rt_device_pwm parent;
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TIM_TypeDef *periph;
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rt_uint8_t channel[4];
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char *name;
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};
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/*
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* channel = 0xFF: the channel is not use.
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*/
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struct rtdevice_pwm_device pwm_device_list[] =
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{
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#ifdef BSP_USING_TIM1_PWM
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{
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.periph = TIM1,
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.name = "pwm1",
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#ifdef BSP_USING_TIM1_PWM_CH1
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.channel[0] = TIM_Channel_1,
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#else
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.channel[0] = 0xFF,
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#endif
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#ifdef BSP_USING_TIM1_PWM_CH2
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.channel[1] = TIM_Channel_2,
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#else
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.channel[1] = 0xFF,
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#endif
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#ifdef BSP_USING_TIM1_PWM_CH3
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.channel[2] = TIM_Channel_3,
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#else
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.channel[2] = 0xFF,
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#endif
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#ifdef BSP_USING_TIM1_PWM_CH4
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.channel[3] = TIM_Channel_4,
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#else
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.channel[3] = 0xFF,
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#endif
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},
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#endif
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#ifdef BSP_USING_TIM2_PWM
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{
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.periph = TIM2,
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.name = "pwm2",
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#ifdef BSP_USING_TIM2_PWM_CH1
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.channel[0] = TIM_Channel_1,
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#else
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.channel[0] = 0xFF,
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#endif
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#ifdef BSP_USING_TIM2_PWM_CH2
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.channel[1] = TIM_Channel_2,
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#else
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.channel[1] = 0xFF,
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#endif
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#ifdef BSP_USING_TIM2_PWM_CH3
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.channel[2] = TIM_Channel_3,
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#else
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.channel[2] = 0xFF,
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#endif
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#ifdef BSP_USING_TIM2_PWM_CH4
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.channel[3] = TIM_Channel_4,
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#else
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.channel[3] = 0xFF,
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#endif
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},
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#endif
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#ifdef BSP_USING_TIM3_PWM
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{
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.periph = TIM3,
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.name = "pwm3",
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#ifdef BSP_USING_TIM3_PWM_CH1
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.channel[0] = TIM_Channel_1,
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#else
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.channel[0] = 0xFF,
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#endif
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#ifdef BSP_USING_TIM3_PWM_CH2
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.channel[1] = TIM_Channel_2,
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#else
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.channel[1] = 0xFF,
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#endif
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#ifdef BSP_USING_TIM3_PWM_CH3
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.channel[2] = TIM_Channel_3,
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#else
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.channel[2] = 0xFF,
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#endif
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#ifdef BSP_USING_TIM3_PWM_CH4
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.channel[3] = TIM_Channel_4,
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#else
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.channel[3] = 0xFF,
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#endif
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},
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#endif
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#ifdef BSP_USING_TIM4_PWM
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{
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.periph = TIM4,
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.name = "pwm4",
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#ifdef BSP_USING_TIM4_PWM_CH1
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.channel[0] = TIM_Channel_1,
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#else
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.channel[0] = 0xFF,
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#endif
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#ifdef BSP_USING_TIM4_PWM_CH2
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.channel[1] = TIM_Channel_2,
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#else
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.channel[1] = 0xFF,
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#endif
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#ifdef BSP_USING_TIM4_PWM_CH3
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.channel[2] = TIM_Channel_3,
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#else
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.channel[2] = 0xFF,
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#endif
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#ifdef BSP_USING_TIM4_PWM_CH4
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.channel[3] = TIM_Channel_4,
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#else
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.channel[3] = 0xFF,
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#endif
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},
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#endif
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};
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static rt_err_t ch32f1_pwm_device_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable)
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{
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struct rtdevice_pwm_device *pwm_device;
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rt_uint32_t channel_index;
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rt_uint16_t ccx_state;
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pwm_device = (struct rtdevice_pwm_device *)device;
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channel_index = configuration->channel;
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if (enable == RT_TRUE)
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{
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ccx_state = TIM_CCx_Enable;
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}
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else
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{
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ccx_state = TIM_CCx_Disable;
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}
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if (channel_index <= 4 && channel_index > 0)
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{
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if (pwm_device->channel[channel_index - 1] == 0xFF)
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return RT_EINVAL;
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TIM_CCxCmd(pwm_device->periph, pwm_device->channel[channel_index - 1], ccx_state);
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}
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else
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{
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return RT_EINVAL;
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}
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TIM_Cmd(pwm_device->periph, ENABLE);
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return RT_EOK;
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}
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static rt_err_t ch32f1_pwm_device_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
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{
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struct rtdevice_pwm_device *pwm_device;
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rt_uint32_t arr_counter, ccr_counter, prescaler, sample_freq;
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rt_uint32_t channel_index;
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rt_uint32_t tim_clock;
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pwm_device = (struct rtdevice_pwm_device *)device;
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tim_clock = ch32f1_tim_clock_get(pwm_device->periph);
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channel_index = configuration->channel;
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arr_counter = pwm_device->periph->ATRLR + 1;
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prescaler = pwm_device->periph->PSC + 1;
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sample_freq = (tim_clock / prescaler) / arr_counter;
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/* unit:ns */
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configuration->period = 1000000000 / sample_freq;
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if (channel_index == 1)
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{
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ccr_counter = pwm_device->periph->CH1CVR + 1;
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configuration->pulse = ((ccr_counter * 100) / arr_counter) * configuration->period / 100;
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}
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else if (channel_index == 2)
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{
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ccr_counter = pwm_device->periph->CH2CVR + 1;
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configuration->pulse = ((ccr_counter * 100) / arr_counter) * configuration->period / 100;
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}
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else if (channel_index == 3)
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{
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ccr_counter = pwm_device->periph->CH3CVR + 1;
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configuration->pulse = ((ccr_counter * 100) / arr_counter) * configuration->period / 100;
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}
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else if (channel_index == 4)
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{
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ccr_counter = pwm_device->periph->CH4CVR + 1;
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configuration->pulse = ((ccr_counter * 100) / arr_counter) * configuration->period / 100;
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}
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else
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return RT_EINVAL;
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return RT_EOK;
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}
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static rt_err_t ch32f1_pwm_device_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
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{
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struct rtdevice_pwm_device *pwm_device;
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rt_uint32_t arr_counter, ccr_counter, prescaler, sample_freq;
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rt_uint32_t channel_index;
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rt_uint32_t tim_clock;
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TIM_TimeBaseInitTypeDef TIM_TimeBaseInitType;
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TIM_OCInitTypeDef TIM_OCInitType;
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pwm_device = (struct rtdevice_pwm_device *)device;
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tim_clock = ch32f1_tim_clock_get(pwm_device->periph);
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channel_index = configuration->channel;
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/* change to freq, unit:Hz */
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sample_freq = 1000000000 / configuration->period;
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/*counter = (tim_clk / prescaler) / sample_freq */
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/*normally, tim_clk is not need div, if arr_counter over 65536, need div.*/
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prescaler = 1;
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arr_counter = (tim_clock / prescaler) / sample_freq;
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if (arr_counter > MAX_COUNTER)
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{
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/* need div tim_clock
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* and round up the prescaler value.
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* (tim_clock >> 16) = tim_clock / 65536
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*/
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if ((tim_clock >> 16) % sample_freq == 0)
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prescaler = (tim_clock >> 16) / sample_freq;
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else
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prescaler = (tim_clock >> 16) / sample_freq + 1;
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/*counter = (tim_clk / prescaler) / sample_freq */
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arr_counter = (tim_clock / prescaler) / sample_freq;
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}
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/* ccr_counter = duty cycle * arr_counter */
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ccr_counter = (configuration->pulse * 100 / configuration->period) * arr_counter / 100;
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/* check arr_counter > 1, cxx_counter > 1 */
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if (arr_counter < MIN_COUNTER)
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{
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arr_counter = MIN_COUNTER;
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}
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if (ccr_counter < MIN_PULSE)
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{
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ccr_counter = MIN_PULSE;
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}
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/* TMRe base configuration */
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TIM_TimeBaseStructInit(&TIM_TimeBaseInitType);
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TIM_TimeBaseInitType.TIM_Period = arr_counter - 1;
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TIM_TimeBaseInitType.TIM_Prescaler = prescaler - 1;
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TIM_TimeBaseInitType.TIM_ClockDivision = TIM_CKD_DIV1;
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TIM_TimeBaseInitType.TIM_CounterMode = TIM_CounterMode_Up;
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TIM_TimeBaseInit(pwm_device->periph, &TIM_TimeBaseInitType);
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TIM_OCStructInit(&TIM_OCInitType);
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TIM_OCInitType.TIM_OCMode = TIM_OCMode_PWM1;
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TIM_OCInitType.TIM_OutputState = TIM_OutputState_Enable;
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TIM_OCInitType.TIM_Pulse = ccr_counter - 1;
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TIM_OCInitType.TIM_OCPolarity = TIM_OCPolarity_High;
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if (channel_index == 1)
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{
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TIM_OC1Init(pwm_device->periph, &TIM_OCInitType);
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TIM_OC1PreloadConfig(pwm_device->periph, TIM_OCPreload_Disable);
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}
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else if (channel_index == 2)
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{
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TIM_OC2Init(pwm_device->periph, &TIM_OCInitType);
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TIM_OC2PreloadConfig(pwm_device->periph, TIM_OCPreload_Disable);
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}
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else if (channel_index == 3)
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{
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TIM_OC3Init(pwm_device->periph, &TIM_OCInitType);
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TIM_OC3PreloadConfig(pwm_device->periph, TIM_OCPreload_Disable);
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}
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else if (channel_index == 4)
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{
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TIM_OC4Init(pwm_device->periph, &TIM_OCInitType);
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TIM_OC4PreloadConfig(pwm_device->periph, TIM_OCPreload_Disable);
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}
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else
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{
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return RT_EINVAL;
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}
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TIM_ARRPreloadConfig(pwm_device->periph, ENABLE);
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TIM_CtrlPWMOutputs(pwm_device->periph, ENABLE);
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return RT_EOK;
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}
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static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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struct rt_pwm_configuration *configuration;
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configuration = (struct rt_pwm_configuration *)arg;
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switch (cmd)
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{
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case PWM_CMD_ENABLE:
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return ch32f1_pwm_device_enable(device, configuration, RT_TRUE);
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case PWM_CMD_DISABLE:
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return ch32f1_pwm_device_enable(device, configuration, RT_FALSE);
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case PWM_CMD_SET:
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return ch32f1_pwm_device_set(device, configuration);
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case PWM_CMD_GET:
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return ch32f1_pwm_device_get(device, configuration);
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default:
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return RT_EINVAL;
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}
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}
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static struct rt_pwm_ops pwm_ops =
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{
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.control = drv_pwm_control};
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static int rt_hw_pwm_init(void)
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{
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int result = RT_EOK;
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int index = 0;
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int channel_index;
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for (index = 0; index < ITEM_NUM(pwm_device_list); index++)
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{
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ch32f1_tim_clock_init(pwm_device_list[index].periph);
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for (channel_index = 0; channel_index < sizeof(pwm_device_list[index].channel); channel_index++)
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{
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|
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if (pwm_device_list[index].channel[channel_index] != 0xFF)
|
|
|
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{
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|
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ch32f1_pwm_io_init(pwm_device_list[index].periph, pwm_device_list[index].channel[channel_index]);
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|
|
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}
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}
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|
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if (rt_device_pwm_register(&pwm_device_list[index].parent, pwm_device_list[index].name, &pwm_ops, RT_NULL) == RT_EOK)
|
|
|
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{
|
|
|
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LOG_D("%s register success", pwm_device_list[index].name);
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|
|
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}
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else
|
|
|
|
{
|
|
|
|
LOG_D("%s register failed", pwm_device_list[index].name);
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|
|
|
result = -RT_ERROR;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
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|
|
|
|
|
|
INIT_BOARD_EXPORT(rt_hw_pwm_init);
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|
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|
|
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#endif /* BSP_USING_PWM */
|