421 lines
11 KiB
C
421 lines
11 KiB
C
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/* ------------------------------------------
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* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1) Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* \version 2016.05
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* \date 2014-07-15
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* \author Wayne Ren(Wei.Ren@synopsys.com)
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--------------------------------------------- */
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/**
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* \file
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* \ingroup ARC_HAL_MISC_CACHE
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* \brief implementation of cache related functions
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*/
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#include "inc/arc/arc_cache.h"
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#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
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struct cache_config {
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uint8_t ver; /* version */
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uint8_t assoc; /* Cache Associativity */
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uint16_t line; /* cache line/block size */
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uint32_t capacity; /* capacity */
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};
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static struct cache_config icache_config, dcache_config;
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/**
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* \brief invalidate multi instruction cache lines
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*
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* \param[in] start_addr start address in instruction cache
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* \param[in] size the bytes to be invalidated
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* \return 0, succeeded, -1, failed
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*/
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int32_t icache_invalidate_mlines(uint32_t start_addr, uint32_t size)
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{
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if (!icache_available()) return -1;
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if ((size == 0) || (size > icache_config.capacity)) {
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return -1;
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}
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uint32_t end_addr;
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uint32_t line_size;
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uint32_t status;
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line_size = (uint32_t)(icache_config.line);
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end_addr = start_addr + size - 1;
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start_addr &= (uint32_t)(~(line_size - 1));
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status = cpu_lock_save();
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do {
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_arc_aux_write(AUX_IC_IVIL, start_addr);
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Asm("nop_s");
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Asm("nop_s");
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Asm("nop_s");
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start_addr += line_size;
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} while (start_addr <= end_addr);
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cpu_unlock_restore(status);
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return 0;
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}
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/**
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* \brief lock multi lines in instruction cache
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*
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* \param[in] start_addr start address in instruction cache
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* \param[in] size the bytes to be locked
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* \return 0, succeeded, -1, failed (cache already locked or other reasons)
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*/
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int32_t icache_lock_mlines(uint32_t start_addr, uint32_t size)
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{
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if (!icache_available()) return -1;
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if ((size == 0) || (size > icache_config.capacity)) {
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return -1;
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}
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uint32_t end_addr;
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uint32_t line_size;
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uint32_t status;
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int32_t ercd = 0;
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line_size = (uint32_t)(icache_config.line);
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end_addr = start_addr + size - 1;
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start_addr &= (uint32_t)(~(line_size - 1));
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status = cpu_lock_save();
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do {
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_arc_aux_write(AUX_IC_LIL, start_addr);
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if(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) {
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start_addr += line_size;
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} else {
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ercd = -1; /* the operation failed */
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break;
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}
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} while (start_addr <= end_addr);
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cpu_unlock_restore(status);
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return ercd;
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}
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/**
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* \brief directly write icache internal ram
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*
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* \param[in] cache_addr, icache internal address(way+index+offset)
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* \param[in] tag cache tag to write (tag+lock bit+valid bit)
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* \param[in] data cache data to write
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* \return 0, succeeded, -1, failed
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*/
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int32_t icache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data)
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{
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if (!icache_available()) return -1;
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if (_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS) {
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return -1;
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}
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_arc_aux_write(AUX_IC_RAM_ADDR, cache_addr);
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_arc_aux_write(AUX_IC_TAG, tag );
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_arc_aux_write(AUX_IC_DATA, data);
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return 0;
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}
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/**
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* \brief directly read icache internal ram
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*
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* \param[in] cache_addr, icache internal address(way+index+offset)
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* \param[out] tag cache tag to read (tag+index+lock bit+valid bit)
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* \param[out] data cache data to read
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* \return 0, succeeded, -1, failed
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*/
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int32_t icache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data)
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{
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if (!icache_available()) return -1;
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if (_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS) {
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return -1;
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}
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_arc_aux_write(AUX_IC_RAM_ADDR, cache_addr);
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*tag = _arc_aux_read(AUX_IC_TAG);
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*data = _arc_aux_read(AUX_IC_DATA);
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return 0;
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}
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/**
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* \brief indirectly read icache internal ram
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*
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* \param[in] mem_addr, memory address
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* \param[out] tag cache tag to read
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* \param[out] data cache data to read
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* \return 0, succeeded, -1, failed
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*/
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int32_t icache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data)
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{
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if (!icache_available()) return -1;
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if (!(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS)) {
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return -1;
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}
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_arc_aux_write(AUX_IC_RAM_ADDR, mem_addr);
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if(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) {
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*tag = _arc_aux_read(AUX_IC_TAG);
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*data = _arc_aux_read(AUX_IC_DATA);
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} else {
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return -1; /* the specified memory is not in icache */
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}
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return 0;
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}
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/**
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* \brief invalidate multi data cache lines
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*
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* \param[in] start_addr start address in data cache
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* \param[in] size the bytes to be invalidated
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* \return 0, succeeded, -1, failed
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*/
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int32_t dcache_invalidate_mlines(uint32_t start_addr, uint32_t size)
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{
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if (!dcache_available()) return -1;
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uint32_t end_addr;
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uint32_t line_size;
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uint32_t status;
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if ((size == 0) || (size > dcache_config.capacity)) {
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return -1;
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}
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line_size = (uint32_t)(dcache_config.line);
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end_addr = start_addr + size - 1;
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start_addr &= (uint32_t)(~(line_size - 1));
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status = cpu_lock_save();
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do {
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_arc_aux_write(AUX_DC_IVDL, start_addr);
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Asm("nop_s");
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Asm("nop_s");
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Asm("nop_s");
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/* wait for flush completion */
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while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
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start_addr += line_size;
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} while (start_addr <= end_addr);
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cpu_unlock_restore(status);
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return 0;
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}
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/**
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* \brief flush multi lines in data cache
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*
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* \param[in] start_addr start address
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* \param[in] size the bytes to be flushed
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* \return 0, succeeded, -1, failed
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*/
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int32_t dcache_flush_mlines(uint32_t start_addr, uint32_t size)
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{
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if (!dcache_available()) return -1;
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if ((size == 0) || (size > dcache_config.capacity)) {
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return -1;
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}
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uint32_t end_addr;
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uint32_t line_size;
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uint32_t status;
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line_size = (uint32_t)(dcache_config.line);
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end_addr = start_addr + size - 1;
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start_addr &= (uint32_t)(~(line_size - 1));
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status = cpu_lock_save();
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do {
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_arc_aux_write(AUX_DC_FLDL, start_addr);
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Asm("nop_s");
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Asm("nop_s");
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Asm("nop_s");
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/* wait for flush completion */
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while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
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start_addr += line_size;
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} while (start_addr <= end_addr);
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cpu_unlock_restore(status);
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return 0;
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}
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/**
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* \brief lock multi lines in data cache
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*
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* \param[in] start_addr start address in data cache
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* \param[in] size the bytes to be locked
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* \return 0, succeeded, -1, failed
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*/
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int32_t dcache_lock_mlines(uint32_t start_addr, uint32_t size)
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{
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if (!dcache_available()) return -1;
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if ((size == 0) || (size > dcache_config.capacity)) {
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return -1;
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}
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uint32_t end_addr;
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uint32_t line_size;
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uint32_t status;
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int32_t ercd = 0;
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line_size = (uint32_t)(dcache_config.line);
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end_addr = start_addr + size - 1;
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start_addr &= (uint32_t)(~(line_size - 1));
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status = cpu_lock_save();
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do {
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_arc_aux_write(AUX_DC_LDL, start_addr);
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Asm("nop_s");
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if(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) {
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start_addr += line_size;
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} else {
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ercd = -1; /* the operation failed */
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break;
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}
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} while (start_addr <= end_addr);
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cpu_unlock_restore(status);
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return ercd;
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}
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/**
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* \brief directly write dcache internal ram
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*
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* \param[in] cache_addr, dcache internal address(way+index+offset)
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* \param[in] tag cache tag to write
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* \param[in] data cache data to write
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* \return 0, succeeded, -1, failed
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*/
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int32_t dcache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data)
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{
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if (!dcache_available()) return -1;
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if (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS) {
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return -1;
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}
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_arc_aux_write(AUX_DC_RAM_ADDR, cache_addr);
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_arc_aux_write(AUX_DC_TAG, tag);
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_arc_aux_write(AUX_DC_DATA, data);
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return 0;
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}
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/**
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* \brief directly read dcache internal ram
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*
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* \param[in] cache_addr, dcache internal address(way+index+offset)
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* \param[out] tag cache tag to read
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* \param[out] data cache data to read
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* \return 0, succeeded, -1, failed
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*/
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int32_t dcache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data)
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{
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if (!dcache_available()) return -1;
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if (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS) {
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return -1;
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}
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_arc_aux_write(AUX_DC_RAM_ADDR, cache_addr);
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*tag = _arc_aux_read(AUX_DC_TAG);
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*data = _arc_aux_read(AUX_DC_DATA);
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return 0;
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}
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/**
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* \brief indirectly read dcache internal ram
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*
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* \param[in] mem_addr, memory address(tag+index+offset)
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* \param[out] tag cache tag to read
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* \param[out] data cache data to read
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* \return 0, succeeded, -1, failed
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*/
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int32_t dcache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data)
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{
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if (!dcache_available()) return -1;
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if (!(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS)) {
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
_arc_aux_write(AUX_DC_RAM_ADDR, mem_addr);
|
||
|
|
if(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) {
|
||
|
|
*tag = _arc_aux_read(AUX_DC_TAG);
|
||
|
|
*data = _arc_aux_read(AUX_DC_DATA);
|
||
|
|
} else {
|
||
|
|
return -1; /* the specified memory is not in dcache */
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* \brief initialize cache
|
||
|
|
* 1. invalidate icache and dcache
|
||
|
|
* 2. Only support ARCv2 cache
|
||
|
|
*/
|
||
|
|
void arc_cache_init(void)
|
||
|
|
{
|
||
|
|
uint32_t build_cfg;
|
||
|
|
|
||
|
|
build_cfg = _arc_aux_read(AUX_BCR_D_CACHE);
|
||
|
|
|
||
|
|
dcache_config.ver = build_cfg & 0xff;
|
||
|
|
|
||
|
|
if (dcache_config.ver >= 0x04) { /* ARCv2 */
|
||
|
|
dcache_enable(DC_CTRL_DISABLE_FLUSH_LOCKED |
|
||
|
|
DC_CTRL_INDIRECT_ACCESS | DC_CTRL_INVALID_FLUSH);
|
||
|
|
dcache_invalidate();
|
||
|
|
dcache_config.assoc = 1 << ((build_cfg >> 8) & 0xf);
|
||
|
|
dcache_config.capacity = 512 << ((build_cfg >> 12) & 0xf);
|
||
|
|
dcache_config.line = 16 << ((build_cfg >> 16) & 0xf);
|
||
|
|
}
|
||
|
|
|
||
|
|
build_cfg = _arc_aux_read(AUX_BCR_I_CACHE);
|
||
|
|
|
||
|
|
icache_config.ver = build_cfg & 0xff;
|
||
|
|
|
||
|
|
if (icache_config.ver >= 0x04) { /* ARCv2 */
|
||
|
|
icache_config.assoc = 1 << ((build_cfg >> 8) & 0xf);
|
||
|
|
icache_config.capacity = 512 << ((build_cfg >> 12) & 0xf);
|
||
|
|
icache_config.line = 8 << ((build_cfg >> 16) & 0xf);
|
||
|
|
|
||
|
|
icache_enable(IC_CTRL_IC_ENABLE);
|
||
|
|
icache_invalidate();
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|