168 lines
5.7 KiB
C
168 lines
5.7 KiB
C
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/**
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*****************************************************************************
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* @file cmem7_spi.h
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*
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* @brief CMEM7 SPI header file
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*
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*
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* @version V1.0
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* @date 3. September 2013
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*
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* @note
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*
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*****************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2013 Capital-micro </center></h2>
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*****************************************************************************
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*/
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#ifndef __CMEM7_SPI_H
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#define __CMEM7_SPI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "cmem7.h"
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#include "cmem7_conf.h"
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#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI0) || \
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((PERIPH) == SPI1))
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/** @defgroup SPI_MODE
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* @{
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*/
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#define SPI_MODE_CPOL_0_CPHA_0 0 /*!< CPOL : Idle clock level is low level.
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CPHA : Capture data at the first edge */
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#define SPI_MODE_CPOL_0_CPHA_1 1 /*!< CPOL : Idle clock level is low level.
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CPHA : Capture data at the second edge */
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#define SPI_MODE_CPOL_1_CPHA_0 2 /*!< CPOL : Idle clock level is high level.
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CPHA : Capture data at the first edge */
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#define SPI_MODE_CPOL_1_CPHA_1 3 /*!< CPOL : Idle clock level is high level.
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CPHA : Capture data at the first edge */
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#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_CPOL_0_CPHA_0) || \
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((MODE) == SPI_MODE_CPOL_0_CPHA_1) || \
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((MODE) == SPI_MODE_CPOL_1_CPHA_0) || \
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((MODE) == SPI_MODE_CPOL_1_CPHA_1))
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/**
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* @}
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*/
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/** @defgroup SPI_INT
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* @{
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*/
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#define SPI_INT_RX_FIFO_UNDERFLOW 0x00000001
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#define SPI_INT_RX_FIFO_OVERFLOW 0x00000002
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#define SPI_INT_RX_FIFO_ALMOST_FULL 0x00000004
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#define SPI_INT_TX_FIFO_UNDERFLOW 0x00000008
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#define SPI_INT_TX_FIFO_OVERFLOW 0x00000010
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#define SPI_INT_TX_FIFO_ALMOST_FULL 0x00000020
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#define SPI_INT_DONE 0x00000040
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#define SPI_INT_ALL 0x0000007F
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#define IS_SPI_INT(INT) (((INT) != 0) && (((INT) & ~SPI_INT_ALL) == 0))
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/**
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* @}
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*/
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/**
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* @brief SPI initialization structure
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*/
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typedef struct
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{
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uint8_t SPI_Mode; /*!< indicates SPI's CPOL and CPHA, ref as @ref SPI_MODE */
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BOOL SPI_RxEn; /*!< indicates if SPI receiver is enabled or not */
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uint8_t SPI_BitLength; /*!< bit length while transmitting and receiving */
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uint8_t SPI_Gap; /*!< cycle number between continuous data frame */
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uint8_t SPI_ClockDividor; /*!< SPI clock dividor, 1 / ((1 + DIV) * 2) */
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} SPI_InitTypeDef;
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/**
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* @}
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*/
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/**
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* @brief SPI initialization
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* @note This function should be called at first before any other interfaces.
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* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
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* @param[in] init A pointer to structure SPI_InitTypeDef
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* @retval None
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*/
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void SPI_Init(SPI0_Type* SPIx, SPI_InitTypeDef *init);
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/**
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* @brief Enable or disable SPI.
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* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
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* @param[in] Enable The bit indicates if the specific SPI is enable or not
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* @retval None
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*/
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void SPI_Enable(SPI0_Type* SPIx, BOOL enable);
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/**
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* @brief Enable or disable SPI interrupt.
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* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
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* @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
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* @param[in] Enable The bit indicates if specific interrupts are enable or not
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* @retval None
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*/
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void SPI_EnableInt(SPI0_Type* SPIx, uint32_t Int, BOOL enable);
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/**
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* @brief Check specific interrupts are set or not
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* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
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* @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
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* @retval BOOL The bit indicates if specific interrupts are set or not
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*/
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BOOL SPI_GetIntStatus(SPI0_Type* SPIx, uint32_t Int);
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/**
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* @brief Clear specific interrupts
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* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
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* @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
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* @retval None
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*/
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void SPI_ClearInt(SPI0_Type* SPIx, uint32_t Int);
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/**
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* @brief Read data from SPI FIFO
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* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
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* @param[in] size Expected data size to be read
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* @param[out] data A user-allocated buffer to fetch data to be read
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* @retval uint8_t Actual read data size
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*/
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uint8_t SPI_ReadFifo(SPI0_Type* SPIx, uint8_t size, uint32_t* data);
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/**
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* @brief Write data to SPI FIFO
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* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
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* @param[in] size Expected data size to be written
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* @param[in] data A pointer to the data to be written
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* @retval uint8_t Actual written data size
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*/
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uint8_t SPI_WriteFifo(SPI0_Type* SPIx, uint8_t Size, uint32_t* data);
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/**
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* @brief send a SPI transcation request
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* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
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* @param[in] size Expected data size to be written and read
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* @retval BOOL The bit indicates if the request is sent
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*/
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BOOL SPI_Transcation(SPI0_Type* SPIx, uint8_t size);
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#ifdef __cplusplus
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}
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#endif
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#endif /*__CMEM7_SPI_H */
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