225 lines
6.8 KiB
C
225 lines
6.8 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __RTE_DEVICE_H
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#define __RTE_DEVICE_H
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/* UART Select, UART0-UART7. */
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/* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins
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in the application for enabling according instance. */
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#define RTE_USART0 0
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#define RTE_USART0_DMA_EN 0
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#define RTE_USART1 0
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#define RTE_USART1_DMA_EN 0
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#define RTE_USART2 0
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#define RTE_USART2_DMA_EN 0
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#define RTE_USART3 0
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#define RTE_USART3_DMA_EN 0
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#define RTE_USART4 0
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#define RTE_USART4_DMA_EN 0
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#define RTE_USART5 0
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#define RTE_USART5_DMA_EN 0
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#define RTE_USART6 0
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#define RTE_USART6_DMA_EN 0
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#define RTE_USART7 0
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#define RTE_USART7_DMA_EN 0
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/* USART configuration. */
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#define USART_RX_BUFFER_LEN 64
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#define USART0_RX_BUFFER_ENABLE 0
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#define USART1_RX_BUFFER_ENABLE 0
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#define USART2_RX_BUFFER_ENABLE 0
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#define USART3_RX_BUFFER_ENABLE 0
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#define USART4_RX_BUFFER_ENABLE 0
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#define USART5_RX_BUFFER_ENABLE 0
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#define USART6_RX_BUFFER_ENABLE 0
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#define USART7_RX_BUFFER_ENABLE 0
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#define RTE_USART0_DMA_TX_CH 1
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#define RTE_USART0_DMA_TX_DMA_BASE DMA0
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#define RTE_USART0_DMA_RX_CH 0
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#define RTE_USART0_DMA_RX_DMA_BASE DMA0
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#define RTE_USART1_DMA_TX_CH 3
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#define RTE_USART1_DMA_TX_DMA_BASE DMA0
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#define RTE_USART1_DMA_RX_CH 2
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#define RTE_USART1_DMA_RX_DMA_BASE DMA0
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#define RTE_USART2_DMA_TX_CH 5
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#define RTE_USART2_DMA_TX_DMA_BASE DMA0
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#define RTE_USART2_DMA_RX_CH 4
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#define RTE_USART2_DMA_RX_DMA_BASE DMA0
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#define RTE_USART3_DMA_TX_CH 7
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#define RTE_USART3_DMA_TX_DMA_BASE DMA0
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#define RTE_USART3_DMA_RX_CH 6
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#define RTE_USART3_DMA_RX_DMA_BASE DMA0
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#define RTE_USART4_DMA_TX_CH 9
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#define RTE_USART4_DMA_TX_DMA_BASE DMA0
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#define RTE_USART4_DMA_RX_CH 8
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#define RTE_USART4_DMA_RX_DMA_BASE DMA0
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#define RTE_USART5_DMA_TX_CH 11
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#define RTE_USART5_DMA_TX_DMA_BASE DMA0
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#define RTE_USART5_DMA_RX_CH 10
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#define RTE_USART5_DMA_RX_DMA_BASE DMA0
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#define RTE_USART6_DMA_TX_CH 13
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#define RTE_USART6_DMA_TX_DMA_BASE DMA0
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#define RTE_USART6_DMA_RX_CH 12
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#define RTE_USART6_DMA_RX_DMA_BASE DMA0
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#define RTE_USART7_DMA_TX_CH 15
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#define RTE_USART7_DMA_TX_DMA_BASE DMA0
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#define RTE_USART7_DMA_RX_CH 14
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#define RTE_USART7_DMA_RX_DMA_BASE DMA0
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/* I2C Select, I2C0 -I2C7*/
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/* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins
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in the application for enabling according instance. */
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#define RTE_I2C0 0
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#define RTE_I2C0_DMA_EN 0
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#define RTE_I2C1 0
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#define RTE_I2C1_DMA_EN 0
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#define RTE_I2C2 0
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#define RTE_I2C2_DMA_EN 0
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#define RTE_I2C3 0
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#define RTE_I2C3_DMA_EN 0
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#define RTE_I2C4 0
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#define RTE_I2C4_DMA_EN 0
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#define RTE_I2C5 0
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#define RTE_I2C5_DMA_EN 0
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#define RTE_I2C6 0
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#define RTE_I2C6_DMA_EN 0
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#define RTE_I2C7 0
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#define RTE_I2C7_DMA_EN 0
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/*I2C configuration*/
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#define RTE_I2C0_Master_DMA_BASE DMA0
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#define RTE_I2C0_Master_DMA_CH 1
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#define RTE_I2C1_Master_DMA_BASE DMA0
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#define RTE_I2C1_Master_DMA_CH 3
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#define RTE_I2C2_Master_DMA_BASE DMA0
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#define RTE_I2C2_Master_DMA_CH 5
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#define RTE_I2C3_Master_DMA_BASE DMA0
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#define RTE_I2C3_Master_DMA_CH 7
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#define RTE_I2C4_Master_DMA_BASE DMA0
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#define RTE_I2C4_Master_DMA_CH 9
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#define RTE_I2C5_Master_DMA_BASE DMA0
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#define RTE_I2C5_Master_DMA_CH 11
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#define RTE_I2C6_Master_DMA_BASE DMA0
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#define RTE_I2C6_Master_DMA_CH 13
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#define RTE_I2C7_Master_DMA_BASE DMA0
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#define RTE_I2C7_Master_DMA_CH 15
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/* SPI select, SPI0 - SPI7.*/
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/* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins
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in the application for enabling according instance. */
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#define RTE_SPI0 0
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#define RTE_SPI0_DMA_EN 0
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#define RTE_SPI1 0
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#define RTE_SPI1_DMA_EN 0
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#define RTE_SPI2 0
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#define RTE_SPI2_DMA_EN 0
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#define RTE_SPI3 0
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#define RTE_SPI3_DMA_EN 0
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#define RTE_SPI4 0
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#define RTE_SPI4_DMA_EN 0
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#define RTE_SPI5 0
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#define RTE_SPI5_DMA_EN 0
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#define RTE_SPI6 0
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#define RTE_SPI6_DMA_EN 0
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#define RTE_SPI7 0
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#define RTE_SPI7_DMA_EN 0
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/* SPI configuration. */
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#define RTE_SPI0_SSEL_NUM kSPI_Ssel0
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#define RTE_SPI0_DMA_TX_CH 1
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#define RTE_SPI0_DMA_TX_DMA_BASE DMA0
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#define RTE_SPI0_DMA_RX_CH 0
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#define RTE_SPI0_DMA_RX_DMA_BASE DMA0
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#define RTE_SPI1_SSEL_NUM kSPI_Ssel0
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#define RTE_SPI1_DMA_TX_CH 3
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#define RTE_SPI1_DMA_TX_DMA_BASE DMA0
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#define RTE_SPI1_DMA_RX_CH 2
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#define RTE_SPI1_DMA_RX_DMA_BASE DMA0
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#define RTE_SPI2_SSEL_NUM kSPI_Ssel0
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#define RTE_SPI2_DMA_TX_CH 5
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#define RTE_SPI2_DMA_TX_DMA_BASE DMA0
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#define RTE_SPI2_DMA_RX_CH 4
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#define RTE_SPI2_DMA_RX_DMA_BASE DMA0
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#define RTE_SPI3_SSEL_NUM kSPI_Ssel0
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#define RTE_SPI3_DMA_TX_CH 7
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#define RTE_SPI3_DMA_TX_DMA_BASE DMA0
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#define RTE_SPI3_DMA_RX_CH 6
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#define RTE_SPI3_DMA_RX_DMA_BASE DMA0
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#define RTE_SPI4_SSEL_NUM kSPI_Ssel0
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#define RTE_SPI4_DMA_TX_CH 9
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#define RTE_SPI4_DMA_TX_DMA_BASE DMA0
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#define RTE_SPI4_DMA_RX_CH 8
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#define RTE_SPI4_DMA_RX_DMA_BASE DMA0
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#define RTE_SPI5_SSEL_NUM kSPI_Ssel0
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#define RTE_SPI5_DMA_TX_CH 11
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#define RTE_SPI5_DMA_TX_DMA_BASE DMA0
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#define RTE_SPI5_DMA_RX_CH 10
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#define RTE_SPI5_DMA_RX_DMA_BASE DMA0
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#define RTE_SPI6_SSEL_NUM kSPI_Ssel0
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#define RTE_SPI6_DMA_TX_CH 13
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#define RTE_SPI6_DMA_TX_DMA_BASE DMA0
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#define RTE_SPI6_DMA_RX_CH 12
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#define RTE_SPI6_DMA_RX_DMA_BASE DMA0
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#define RTE_SPI7_SSEL_NUM kSPI_Ssel0
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#define RTE_SPI7_DMA_TX_CH 15
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#define RTE_SPI7_DMA_TX_DMA_BASE DMA0
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#define RTE_SPI7_DMA_RX_CH 14
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#define RTE_SPI7_DMA_RX_DMA_BASE DMA0
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#endif /* __RTE_DEVICE_H */
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