322 lines
12 KiB
C
322 lines
12 KiB
C
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/**
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******************************************************************************
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* @brief DMA header file of the firmware library.
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __GD32F10X_DMA_H
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#define __GD32F10X_DMA_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "gd32f10x.h"
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/** @addtogroup GD32F10x_Firmware
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* @{
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*/
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/** @addtogroup DMA
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* @{
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*/
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/** @defgroup DMA_Exported_Types
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* @{
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*/
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/**
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* @brief DMA Initial Parameters
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*/
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typedef struct {
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uint32_t DMA_PeripheralBaseAddr; /*!< The base address of the peripheral. */
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uint32_t DMA_MemoryBaseAddr; /*!< The base address of the memory. */
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uint32_t DMA_DIR; /*!< The direction of data transmission.
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detailed in @ref DMA_data_transfer_direction */
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uint32_t DMA_BufferSize; /*!< The buffer size of data transmission. */
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uint32_t DMA_PeripheralInc; /*!< The incremented_mode of the Peripheral address register.
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detailed in @ref DMA_peripheral_Address_incremented_mode */
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uint32_t DMA_MemoryInc; /*!< The incremented_mode of the memory address register.
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detailed in @ref DMA_memory_Address_incremented_mode */
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uint32_t DMA_PeripheralDataSize; /*!< The data transmission width of Peripheral.
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detailed in @ref DMA_peripheral_data_size */
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uint32_t DMA_MemoryDataSize; /*!< The data transmission width of Memory.
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detailed in @ref DMA_memory_data_size */
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uint32_t DMA_Mode; /*!< The mode of circular transmission.
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detailed in @ref DMA_circular_normal_mode */
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uint32_t DMA_Priority; /*!< The software priority for the DMAy Channelx.
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detailed in @ref DMA_priority_level */
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uint32_t DMA_MTOM; /*!< The mode of memory-to-memory transfer.
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detailed in @ref DMA_memory_to_memory */
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} DMA_InitPara;
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/**
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* @}
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*/
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/** @defgroup DMA_Exported_Constants
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* @{
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*/
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/** @defgroup DMA_data_transfer_direction
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* @{
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*/
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#define DMA_DIR_PERIPHERALDST DMA_CTLR_DIR
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#define DMA_DIR_PERIPHERALSRC ((uint32_t)0x00000000)
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/**
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* @}
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*/
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/** @defgroup DMA_peripheral_Address_Increasing_mode
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* @{
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*/
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#define DMA_PERIPHERALINC_ENABLE DMA_CTLR_PNAGA
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#define DMA_PERIPHERALINC_DISABLE ((uint32_t)0x00000000)
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/**
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* @}
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*/
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/** @defgroup DMA_memory_Address_Increasing_mode
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* @{
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*/
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#define DMA_MEMORYINC_ENABLE DMA_CTLR_MNAGA
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#define DMA_MEMORYINC_DISABLE ((uint32_t)0x00000000)
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/**
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* @}
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*/
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/** @defgroup DMA_peripheral_data_size
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* @{
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*/
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#define DMA_PERIPHERALDATASIZE_BYTE ((uint32_t)0x00000000)
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#define DMA_PERIPHERALDATASIZE_HALFWORD DMA_CTLR_PSIZE_0
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#define DMA_PERIPHERALDATASIZE_WORD DMA_CTLR_PSIZE_1
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/**
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* @}
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*/
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/** @defgroup DMA_memory_data_size
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* @{
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*/
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#define DMA_MEMORYDATASIZE_BYTE ((uint32_t)0x00000000)
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#define DMA_MEMORYDATASIZE_HALFWORD DMA_CTLR_MSIZE_0
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#define DMA_MEMORYDATASIZE_WORD DMA_CTLR_MSIZE_1
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/**
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* @}
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*/
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/** @defgroup DMA_circular_normal_mode
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* @{
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*/
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#define DMA_MODE_CIRCULAR DMA_CTLR_CIRC
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#define DMA_MODE_NORMAL ((uint32_t)0x00000000)
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/**
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* @}
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*/
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/** @defgroup DMA_priority_level
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* @{
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*/
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#define DMA_PRIORITY_VERYHIGH DMA_CTLR_PRIO
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#define DMA_PRIORITY_HIGH DMA_CTLR_PRIO_1
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#define DMA_PRIORITY_MEDIUM DMA_CTLR_PRIO_0
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#define DMA_PRIORITY_LOW ((uint32_t)0x00000000)
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/**
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* @}
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*/
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/** @defgroup DMA_memory_to_memory
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* @{
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*/
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#define DMA_MEMTOMEM_ENABLE DMA_CTLR_MEMTOMEM
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#define DMA_MEMTOMEM_DISABLE ((uint32_t)0x00000000)
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/**
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* @}
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*/
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/** @defgroup DMA_interrupts_definition
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* @{
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*/
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#define DMA_INT_TC DMA_CTLR_TCIE
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#define DMA_INT_HT DMA_CTLR_HTIE
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#define DMA_INT_ERR DMA_CTLR_ERRIE
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#define DMA1_INT_GL1 DMA_IFR_GIF1
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#define DMA1_INT_TC1 DMA_IFR_TCIF1
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#define DMA1_INT_HT1 DMA_IFR_HTIF1
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#define DMA1_INT_ERR1 DMA_IFR_ERRIF1
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#define DMA1_INT_GL2 DMA_IFR_GIF2
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#define DMA1_INT_TC2 DMA_IFR_TCIF2
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#define DMA1_INT_HT2 DMA_IFR_HTIF2
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#define DMA1_INT_ERR2 DMA_IFR_ERRIF2
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#define DMA1_INT_GL3 DMA_IFR_GIF3
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#define DMA1_INT_TC3 DMA_IFR_TCIF3
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#define DMA1_INT_HT3 DMA_IFR_HTIF3
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#define DMA1_INT_ERR3 DMA_IFR_ERRIF3
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#define DMA1_INT_GL4 DMA_IFR_GIF4
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#define DMA1_INT_TC4 DMA_IFR_TCIF4
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#define DMA1_INT_HT4 DMA_IFR_HTIF4
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#define DMA1_INT_ERR4 DMA_IFR_ERRIF4
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#define DMA1_INT_GL5 DMA_IFR_GIF5
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#define DMA1_INT_TC5 DMA_IFR_TCIF5
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#define DMA1_INT_HT5 DMA_IFR_HTIF5
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#define DMA1_INT_ERR5 DMA_IFR_ERRIF5
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#define DMA1_INT_GL6 DMA_IFR_GIF6
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#define DMA1_INT_TC6 DMA_IFR_TCIF6
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#define DMA1_INT_HT6 DMA_IFR_HTIF6
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#define DMA1_INT_ERR6 DMA_IFR_ERRIF6
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#define DMA1_INT_GL7 DMA_IFR_GIF7
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#define DMA1_INT_TC7 DMA_IFR_TCIF7
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#define DMA1_INT_HT7 DMA_IFR_HTIF7
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#define DMA1_INT_ERR7 DMA_IFR_ERRIF7
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#define DMA2_INT_GL1 ((uint32_t)0x10000001)
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#define DMA2_INT_TC1 ((uint32_t)0x10000002)
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#define DMA2_INT_HT1 ((uint32_t)0x10000004)
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#define DMA2_INT_TE1 ((uint32_t)0x10000008)
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#define DMA2_INT_GL2 ((uint32_t)0x10000010)
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#define DMA2_INT_TC2 ((uint32_t)0x10000020)
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#define DMA2_INT_HT2 ((uint32_t)0x10000040)
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#define DMA2_INT_TE2 ((uint32_t)0x10000080)
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#define DMA2_INT_GL3 ((uint32_t)0x10000100)
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#define DMA2_INT_TC3 ((uint32_t)0x10000200)
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#define DMA2_INT_HT3 ((uint32_t)0x10000400)
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#define DMA2_INT_TE3 ((uint32_t)0x10000800)
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#define DMA2_INT_GL4 ((uint32_t)0x10001000)
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#define DMA2_INT_TC4 ((uint32_t)0x10002000)
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#define DMA2_INT_HT4 ((uint32_t)0x10004000)
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#define DMA2_INT_TE4 ((uint32_t)0x10008000)
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#define DMA2_INT_GL5 ((uint32_t)0x10010000)
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#define DMA2_INT_TC5 ((uint32_t)0x10020000)
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#define DMA2_INT_HT5 ((uint32_t)0x10040000)
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#define DMA2_INT_TE5 ((uint32_t)0x10080000)
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/**
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* @}
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*/
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/** @defgroup DMA_flags_definition
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* @{
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*/
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#define DMA1_FLAG_GL1 DMA_IFR_GIF1
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#define DMA1_FLAG_TC1 DMA_IFR_TCIF1
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#define DMA1_FLAG_HT1 DMA_IFR_HTIF1
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#define DMA1_FLAG_ERR1 DMA_IFR_ERRIF1
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#define DMA1_FLAG_GL2 DMA_IFR_GIF2
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#define DMA1_FLAG_TC2 DMA_IFR_TCIF2
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#define DMA1_FLAG_HT2 DMA_IFR_HTIF2
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#define DMA1_FLAG_ERR2 DMA_IFR_ERRIF2
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#define DMA1_FLAG_GL3 DMA_IFR_GIF3
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#define DMA1_FLAG_TC3 DMA_IFR_TCIF3
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#define DMA1_FLAG_HT3 DMA_IFR_HTIF3
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#define DMA1_FLAG_ERR3 DMA_IFR_ERRIF3
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#define DMA1_FLAG_GL4 DMA_IFR_GIF4
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#define DMA1_FLAG_TC4 DMA_IFR_TCIF4
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#define DMA1_FLAG_HT4 DMA_IFR_HTIF4
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#define DMA1_FLAG_ERR4 DMA_IFR_ERRIF4
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#define DMA1_FLAG_GL5 DMA_IFR_GIF5
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#define DMA1_FLAG_TC5 DMA_IFR_TCIF5
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#define DMA1_FLAG_HT5 DMA_IFR_HTIF5
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#define DMA1_FLAG_ERR5 DMA_IFR_ERRIF5
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#define DMA1_FLAG_GL6 DMA_IFR_GIF6
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#define DMA1_FLAG_TC6 DMA_IFR_TCIF6
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#define DMA1_FLAG_HT6 DMA_IFR_HTIF6
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#define DMA1_FLAG_ERR6 DMA_IFR_ERRIF6
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#define DMA1_FLAG_GL7 DMA_IFR_GIF7
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#define DMA1_FLAG_TC7 DMA_IFR_TCIF7
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#define DMA1_FLAG_HT7 DMA_IFR_HTIF7
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#define DMA1_FLAG_ERR7 DMA_IFR_ERRIF7
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#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
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#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
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#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
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#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
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#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
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#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
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#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
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#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
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#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
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#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
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#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
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#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
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#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
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#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
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#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
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#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
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#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
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#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
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#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
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#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @defgroup DMA_Exported_Functions
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* @{
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*/
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/* Function used to reset the DMA configuration */
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void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx);
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/* The functions of Initialization and Configuration */
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void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitPara *DMA_InitParaStruct);
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void DMA_ParaInit(DMA_InitPara *DMA_InitParaStruct);
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void DMA_Enable(DMA_Channel_TypeDef *DMAy_Channelx, TypeState NewValue);
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/* The functions of Data Counter */
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void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber);
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uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx);
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/* The functions of Interrupts and flags management */
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void DMA_INTConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_INT, TypeState NewValue);
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TypeState DMA_GetBitState(uint32_t DMA_FLAG);
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void DMA_ClearBitState(uint32_t DMA_FLAG);
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TypeState DMA_GetIntBitState(uint32_t DMA_INT);
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void DMA_ClearIntBitState(uint32_t DMA_INT);
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#ifdef __cplusplus
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}
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#endif
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#endif /*__GD32F10x_DMA_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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