426 lines
11 KiB
C
426 lines
11 KiB
C
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2017-10-10 Tanek the first version
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* 2019-5-10 misonyo add DMA TX and RX function
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* 2020-10-14 wangqiang use phy device in phy monitor thread
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* 2022-08-29 xjy198903 add 1170 rgmii support
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#ifdef RT_USING_FINSH
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#include <finsh.h>
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#endif
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#include "fsl_enet.h"
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#ifdef RT_USING_LWIP
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#include <netif/ethernetif.h>
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#include "lwipopts.h"
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#define DBG_TAG "drv.eth"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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/* The PHY ID one register */
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#define PHY_ID1_REG 0x02U
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/* The PHY ID two register */
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#define PHY_ID2_REG 0x03U
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/* The PHY auto-negotiate advertise register */
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#define PHY_AUTONEG_ADVERTISE_REG 0x04U
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/* The PHY basic control register */
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#define PHY_BASIC_CONTROL_REG 0x00U
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#define PHY_RESET_MASK (1<<15)
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#define PHY_AUTO_NEGOTIATION_MASK (1<<12)
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#define PHY_LINK (1 << 0)
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#define PHY_100M (1 << 1)
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#define PHY_FULL_DUPLEX (1 << 2)
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/* The PHY basic status register */
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#define PHY_BASIC_STATUS_REG 0x01U
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#define PHY_LINKED_STATUS_MASK (1<<2)
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#define PHY_AUTONEGO_COMPLETE_MASK (1<<5)
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/* The PHY status register. */
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#define PHY_Status_REG 0x1FU
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#define PHY_100M_MASK (1<<3)
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#define PHY_FULL_DUPLEX_MASK (1<<4)
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#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
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#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
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//extern phy_lan8741_resource_t g_phy_resource;
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#define EXAMPLE_ENET_BASE ENET0
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#define EXAMPLE_PHY_ADDRESS 0x00U
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#define ENET_EXAMPLE_IRQ ETHERNET_IRQn
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#define EXAMPLE_CLOCK_FREQ (50000000U)
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#define ENET_RXBD_NUM (4)
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#define ENET_TXBD_NUM (4)
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#define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
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#define ENET_BuffSizeAlign(n) ENET_ALIGN(n, ENET_BUFF_ALIGNMENT)
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#define ENET_ALIGN(x, align) ((unsigned int)((x) + ((align)-1)) & (unsigned int)(~(unsigned int)((align)-1)))
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rt_align(4) enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM];
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rt_align(4) enet_tx_bd_struct_t g_txBuffDescrip[ENET_RXBD_NUM];
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static enet_tx_reclaim_info_t g_txDirty[ENET_TXBD_NUM];
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#define MAX_ADDR_LEN 6
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struct rt_stm32_eth
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{
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/* inherit from ethernet device */
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struct eth_device parent;
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#ifndef PHY_USING_INTERRUPT_MODE
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rt_timer_t poll_link_timer;
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#endif
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/* interface address info, hw address */
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rt_uint8_t dev_addr[MAX_ADDR_LEN];
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enet_handle_t g_handle;
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rt_uint32_t rx_channel;
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};
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static struct rt_stm32_eth stm32_eth_device;
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static void ENET_IntCallback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, uint8_t channel, enet_tx_reclaim_info_t *txReclaimInfo, void *param)
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{
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rt_err_t result;
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switch (event)
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{
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case kENET_TxIntEvent:
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/* Get frame info after whole frame transmits out */
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// if (txReclaimInfo != NULL)
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// {
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// rt_free((*txReclaimInfo).context);
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// }
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break;
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case kENET_RxIntEvent:
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stm32_eth_device.rx_channel = channel;
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result = eth_device_ready(&(stm32_eth_device.parent));
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if (result != RT_EOK)
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{
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LOG_I("_enet_rx_data err = %d", result);
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}
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default:
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break;
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}
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}
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static rt_err_t rt_stm32_eth_init(rt_device_t dev)
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{
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uint32_t count = 0;
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bool link = false;
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bool autonego = false;
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status_t status;
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enet_config_t config;
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int i;
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uint32_t rxbuffer[ENET_RXBD_NUM];
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struct rt_stm32_eth *eth = (struct rt_stm32_eth*)dev->user_data;
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for (i = 0; i < ENET_RXBD_NUM; i++)
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{
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/* This is for rx buffers, static alloc and dynamic alloc both ok. use as your wish. */
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rxbuffer[i] = (uint32_t)rt_malloc(ENET_RXBUFF_SIZE);
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}
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/* prepare the buffer configuration. */
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enet_buffer_config_t buffConfig[1] = {{
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ENET_RXBD_NUM,
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ENET_TXBD_NUM,
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&g_txBuffDescrip[0],
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&g_txBuffDescrip[0],
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&g_txDirty[0],
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&g_rxBuffDescrip[0],
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&g_rxBuffDescrip[ENET_RXBD_NUM],
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&rxbuffer[0],
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ENET_BuffSizeAlign(ENET_RXBUFF_SIZE),
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}};
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CLOCK_AttachClk(kNONE_to_ENETRMII);
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CLOCK_EnableClock(kCLOCK_Enet);
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ENET_SetSMI(EXAMPLE_ENET_BASE, CLOCK_GetCoreSysClkFreq());
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ENET_GetDefaultConfig(&config);
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/* Use the actual speed and duplex when phy success to finish the autonegotiation. */
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config.miiSpeed = kENET_MiiSpeed100M;
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config.miiDuplex = kENET_MiiFullDuplex;
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config.interrupt = (kENET_DmaRx) | (kENET_DmaTx);
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ENET_Init(EXAMPLE_ENET_BASE, &config, &stm32_eth_device.dev_addr[0], EXAMPLE_CLOCK_FREQ);
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ENET_DescriptorInit(EXAMPLE_ENET_BASE, &config, &buffConfig[0]);
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ENET_CreateHandler(EXAMPLE_ENET_BASE, ð->g_handle, &config, &buffConfig[0], ENET_IntCallback, NULL);
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ENET_StartRxTx(EXAMPLE_ENET_BASE, 1, 1);
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return RT_EOK;
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}
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static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
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{
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switch (cmd)
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{
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case NIOCTL_GADDR:
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/* get mac address */
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if (args)
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{
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SMEMCPY(args, stm32_eth_device.dev_addr, 6);
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}
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else
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{
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return -RT_ERROR;
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}
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break;
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default :
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break;
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}
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return RT_EOK;
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}
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rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
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{
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struct pbuf *q;
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status_t status;
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struct rt_stm32_eth *eth = (struct rt_stm32_eth*)dev->user_data;
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// LOG_D("rt_stm32_eth_tx: len: %d, tot_len:%d", p->len, p->tot_len);
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enet_buffer_struct_t txBuff[ENET_TXBD_NUM];
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enet_tx_frame_struct_t txFrame = {0};
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for (q = p; q != NULL; q = q->next)
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{
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txBuff[txFrame.txBuffNum].buffer = q->payload;
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txBuff[txFrame.txBuffNum].length = q->len;
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txFrame.txBuffNum++;
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}
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txFrame.txBuffArray = txBuff;
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txFrame.txConfig.intEnable = true;
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txFrame.txConfig.tsEnable = true;
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txFrame.context = RT_NULL;
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status = ENET_SendFrame(EXAMPLE_ENET_BASE, ð->g_handle, &txFrame, 0);
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return (status == kStatus_Success);
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}
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struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
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{
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struct pbuf *p = RT_NULL;
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uint32_t len = 0;
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status_t status;
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struct rt_stm32_eth *eth = (struct rt_stm32_eth*)dev->user_data;
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status = ENET_GetRxFrameSize(EXAMPLE_ENET_BASE, ð->g_handle, &len, eth->rx_channel);
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// LOG_D("rt_stm32_eth_rx: status:%d, length: %d, channel:%d", status, len, eth->rx_channel);
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if (len != 0 && (status == kStatus_Success))
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{
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/* Received valid frame. Deliver the rx buffer with the size equal to length. */
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p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
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if (p != NULL)
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{
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status = ENET_ReadFrame(EXAMPLE_ENET_BASE, ð->g_handle, p->payload, len, eth->rx_channel, NULL);
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if (status == kStatus_Success)
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{
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return p;
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}
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else
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{
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LOG_D(" A frame read failed\n");
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pbuf_free(p);
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}
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}
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else
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{
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LOG_D(" pbuf_alloc faild\n");
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}
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}
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else if (status == kStatus_ENET_RxFrameError)
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{
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/* update the receive buffer. */
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ENET_ReadFrame(EXAMPLE_ENET_BASE, ð->g_handle, NULL, 0, eth->rx_channel, NULL);
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}
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return RT_NULL;
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}
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static void phy_monitor_thread_entry(void *parameter)
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{
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uint8_t phy_addr = 0xFF;
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uint8_t detected_count = 0;
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while(phy_addr == 0xFF)
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{
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/* phy search */
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rt_uint16_t i, temp;
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for (i = 0; i <= 0x1F; i++)
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{
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// EthHandle.Init.PhyAddress = i;
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ENET_MDIORead(EXAMPLE_ENET_BASE, i, PHY_ID1_REG, &temp);
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if (temp != 0xFFFF && temp != 0x00)
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{
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phy_addr = i;
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break;
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}
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}
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detected_count++;
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rt_thread_mdelay(1000);
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if (detected_count > 10)
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{
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LOG_E("No PHY device was detected, please check hardware!");
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}
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}
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LOG_D("Found a phy, address:0x%02X", phy_addr);
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/* RESET PHY */
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LOG_D("RESET PHY!");
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ENET_MDIOWrite(EXAMPLE_ENET_BASE, phy_addr, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK);
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rt_thread_mdelay(2000);
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ENET_MDIOWrite(EXAMPLE_ENET_BASE, phy_addr, PHY_BASIC_CONTROL_REG, PHY_AUTO_NEGOTIATION_MASK);
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while(1)
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{
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static rt_uint8_t phy_speed = 0;
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uint8_t phy_speed_new = 0;
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uint16_t status;
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ENET_MDIORead(EXAMPLE_ENET_BASE, phy_addr, PHY_BASIC_STATUS_REG, &status);
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LOG_D("phy basic status reg is 0x%X", status);
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if (status & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK))
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{
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uint16_t SR = 0;
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phy_speed_new |= PHY_LINK;
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ENET_MDIORead(EXAMPLE_ENET_BASE, phy_addr, PHY_Status_REG, &SR);
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LOG_D("phy control status reg is 0x%X", SR);
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if (PHY_Status_SPEED_100M(SR))
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{
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phy_speed_new |= PHY_100M;
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}
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if (PHY_Status_FULL_DUPLEX(SR))
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{
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phy_speed_new |= PHY_FULL_DUPLEX;
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}
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}
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if (phy_speed != phy_speed_new)
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{
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phy_speed = phy_speed_new;
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if (phy_speed & PHY_LINK)
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{
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LOG_D("link up");
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if (phy_speed & PHY_100M)
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{
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LOG_D("100Mbps");
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}
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else
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{
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LOG_D("10Mbps");
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}
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if (phy_speed & PHY_FULL_DUPLEX)
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{
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LOG_D("full-duplex");
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}
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else
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{
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LOG_D("half-duplex");
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}
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/* send link up. */
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eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
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||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
LOG_I("link down");
|
||
|
|
eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
rt_thread_mdelay(1000);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
static int rt_hw_imxrt_eth_init(void)
|
||
|
|
{
|
||
|
|
rt_err_t state = RT_EOK;
|
||
|
|
|
||
|
|
stm32_eth_device.dev_addr[0] = 0x00;
|
||
|
|
stm32_eth_device.dev_addr[1] = 0x80;
|
||
|
|
stm32_eth_device.dev_addr[2] = 0xE1;
|
||
|
|
stm32_eth_device.dev_addr[3] = 0x01;
|
||
|
|
stm32_eth_device.dev_addr[4] = 0x02;
|
||
|
|
stm32_eth_device.dev_addr[5] = 0x03;
|
||
|
|
|
||
|
|
stm32_eth_device.parent.parent.init = rt_stm32_eth_init;
|
||
|
|
stm32_eth_device.parent.parent.open = RT_NULL;
|
||
|
|
stm32_eth_device.parent.parent.close = RT_NULL;
|
||
|
|
stm32_eth_device.parent.parent.read = RT_NULL;
|
||
|
|
stm32_eth_device.parent.parent.write = RT_NULL;
|
||
|
|
stm32_eth_device.parent.parent.control = rt_stm32_eth_control;
|
||
|
|
stm32_eth_device.parent.parent.user_data = &stm32_eth_device;
|
||
|
|
|
||
|
|
stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx;
|
||
|
|
stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;
|
||
|
|
|
||
|
|
/* register eth device */
|
||
|
|
state = eth_device_init(&(stm32_eth_device.parent), "e0");
|
||
|
|
if (RT_EOK != state)
|
||
|
|
{
|
||
|
|
LOG_E("emac device init faild: %d", state);
|
||
|
|
state = -RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* start phy monitor */
|
||
|
|
rt_thread_startup(rt_thread_create("phy", phy_monitor_thread_entry, RT_NULL, 1024, RT_THREAD_PRIORITY_MAX - 2, 2));
|
||
|
|
return state;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
INIT_DEVICE_EXPORT(rt_hw_imxrt_eth_init);
|
||
|
|
|
||
|
|
#endif
|