160 lines
6.1 KiB
C
160 lines
6.1 KiB
C
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/*
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* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/******************************************************************************
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* @file dw_spi.h
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* @brief header file for spi driver
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* @version V1.0
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* @date 02. June 2017
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******************************************************************************/
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#ifndef __DW_SPI_H
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#define __DW_SPI_H
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#include <stdio.h>
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#include "soc.h"
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/*
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* SPI register bit definitions
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*/
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#define DW_SPI_ENABLE 0x01
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#define DW_SPI_DISABLE 0x00
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#define DW_SPI_TMOD_BIT8 0x0100
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#define DW_SPI_TMOD_BIT9 0x0200
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#define DW_SPI_POLARITY 0x80
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#define DW_SPI_PHASE 0x40
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#define DW_SPI_BUSY 0x01
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#define DW_SPI_TFE 0x04
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#define DW_SPI_RFNE 0x08
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#define DW_SPI_INT_EN 0x19
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#define DW_SPI_RINT_EN 0x3e
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#define DW_SPI_TINT_EN 0x3f
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#define DW_SPI_INT_DISABLE 0x00
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#define DW_SPI_INT_MASK_RX 0x27
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#define DW_SPI_INT_MASKTX 0x3e
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#define DW_SPI_RDMAE 0x1
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#define DW_SPI_TDMAE 0x2
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#define DW_SPI_TXFIFO_LV 0x0
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#define DW_SPI_RXFIFO_LV 0x1d
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#define DW_SPI_RXFIFO_NOT_EMPTY 0x08
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#define DW_SPI_START_RX 0x0
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#define DW_SPI_FIFO_MAX_LV 0x20
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#define DW_SPI_FIFO_OVER_LV 0x18
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#define DW_SPI_RXFIFO_OVERFLOW 0x08
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#define DW_SPI_RXFIFO_FULL 0x10
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#define DW_SPI_TXFIFO_EMPTY 0x01
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#define SPI_CS_SELECTED 0x0
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#define DW_SPI_IMR_TXEIM 0x01 /* Transmit FIFO Empty Interrupt Mask */
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#define DW_SPI_IMR_RXFIM 0x10 /* Receive FIFO Full Interrupt Mask */
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/* some infoermationgs of SPI for special MCU */
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#define DW_SPI_DEFAULT_BAUDR 10000000 /* 10M */
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#define DW_SPI_MAXID 0x1
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#define SPI_INITIALIZED ((uint8_t)(1U)) // SPI initalized
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#define SPI_POWERED ((uint8_t)(1U<< 1)) // SPI powered on
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#define SPI_CONFIGURED ((uint8_t)(1U << 2)) // SPI configured
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#define SPI_DATA_LOST ((uint8_t)(1U << 3)) // SPI data lost occurred
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#define SPI_MODE_FAULT ((uint8_t)(1U << 4)) // SPI mode fault occurred
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typedef enum {
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DWENUM_SPI_DMACR_RXE = 0,
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DWENUM_SPI_DMACR_TXE = 1,
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} DWENUM_SPI_DMACR;
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typedef enum {
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DWENUM_SPI_TXRX = 0,
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DWENUM_SPI_TX = 1,
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DWENUM_SPI_RX = 2,
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DWENUM_SPI_EERX = 3
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} DWENUM_SPI_MODE;
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typedef enum {
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DWENUM_SPI_CLOCK_POLARITY_LOW = 0,
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DWENUM_SPI_CLOCK_POLARITY_HIGH = 1
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} DWENUM_SPI_POLARITY;
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typedef enum {
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DWENUM_SPI_CLOCK_PHASE_MIDDLE = 0,
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DWENUM_SPI_CLOCK_PHASE_START = 1
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} DWENUM_SPI_PHASE;
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typedef enum {
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DWENUM_SPI_DATASIZE_4 = 3,
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DWENUM_SPI_DATASIZE_5 = 4,
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DWENUM_SPI_DATASIZE_6 = 5,
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DWENUM_SPI_DATASIZE_7 = 6,
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DWENUM_SPI_DATASIZE_8 = 7,
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DWENUM_SPI_DATASIZE_9 = 8,
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DWENUM_SPI_DATASIZE_10 = 9,
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DWENUM_SPI_DATASIZE_11 = 10,
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DWENUM_SPI_DATASIZE_12 = 11,
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DWENUM_SPI_DATASIZE_13 = 12,
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DWENUM_SPI_DATASIZE_14 = 13,
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DWENUM_SPI_DATASIZE_15 = 14,
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DWENUM_SPI_DATASIZE_16 = 15
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} DWENUM_SPI_DATAWIDTH;
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typedef enum {
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DWENUM_SPI_CS0 = 1,
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DWENUM_SPI_CS1 = 2
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} DWENUM_SPI_SLAVE;
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typedef struct {
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__IOM uint16_t CTRLR0; /* Offset: 0x000 (R/W) Control register 0 */
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uint16_t RESERVED0;
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__IOM uint16_t CTRLR1; /* Offset: 0x004 (R/W) Control register 1 */
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uint16_t RESERVED1;
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__IOM uint8_t SPIENR; /* Offset: 0x008 (R/W) SSI enable regiseter */
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uint8_t RESERVED2[7];
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__IOM uint32_t SER; /* Offset: 0x010 (R/W) Slave enable register */
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__IOM uint16_t BAUDR; /* Offset: 0x014 (R/W) Baud rate select */
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uint16_t RESERVED3;
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__IOM uint32_t TXFTLR; /* Offset: 0x018 (R/W) Transmit FIFO Threshold Level */
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__IOM uint32_t RXFTLR; /* Offset: 0x01c (R/W) Receive FIFO Threshold Level */
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__IOM uint32_t TXFLR; /* Offset: 0x020 (R/W) Transmit FIFO Level register */
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__IOM uint32_t RXFLR; /* Offset: 0x024 (R/W) Receive FIFO Level Register */
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__IOM uint8_t SR; /* Offset: 0x028 (R/W) status register */
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uint8_t RESERVED4[3];
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__IOM uint32_t IMR; /* Offset: 0x02C (R/W) Interrupt Mask Register */
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__IM uint32_t ISR; /* Offset: 0x030 (R/W) interrupt status register */
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__IM uint32_t RISR; /* Offset: 0x034 (R/W) Raw Interrupt Status Register */
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__IM uint8_t TXOICR; /* Offset: 0x038 (R/W) Transmit FIFO Overflow Interrupt Clear Register */
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uint8_t RESERVED5[3];
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__IM uint8_t RXOICR; /* Offset: 0x03C (R/W) Receive FIFO Overflow Interrupt Clear Register*/
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uint8_t RESERVED6[3];
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__IM uint8_t RXUICR; /* Offset: 0x040 (R/W) Receive FIFO Underflow Interrupt Clear Register */
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uint8_t RESERVED7[3];
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__IM uint8_t MSTICR; /* Offset: 0x044 (R/W) Multi-Master Interrupt Clear Register */
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uint8_t RESERVED8[3];
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__IM uint8_t ICR; /* Offset: 0x048 (R/W) Interrupt Clear Register */
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uint8_t RESERVED9[3];
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__IOM uint8_t DMACR; /* Offset: 0x04C (R/W) DMA Control Register */
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uint8_t RESERVED10[3];
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__IOM uint8_t DMATDLR; /* Offset: 0x050 (R/W) DMA Transmoit Data Level */
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uint8_t RESERVED11[3];
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__IOM uint8_t DMARDLR; /* Offset: 0x054 (R/W) DMA Receive Data Level */
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uint8_t RESERVED12[3];
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__IM uint32_t IDR; /* Offset: 0x058 (R/W) identification register */
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uint32_t RESERVED13;
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__IOM uint16_t DR; /* Offset: 0x060 (R/W) Data Register */
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uint16_t RESERVED14[17];
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__IOM uint8_t WR; /* Offset: 0x0A0 (R/W) SPI is Master or Slave Select Register */
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} dw_spi_reg_t;
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#endif /* __DW_SPI_H */
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