232 lines
6.8 KiB
C
232 lines
6.8 KiB
C
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/**************************************************************************//**
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*
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-8-15 YHKuo First version
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*
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******************************************************************************/
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#include <rtconfig.h>
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#if defined(BSP_USING_EPWM)
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#define LOG_TAG "drv.epwm"
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#define DBG_ENABLE
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#define DBG_SECTION_NAME LOG_TAG
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#define DBG_LEVEL DBG_INFO
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#define DBG_COLOR
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#include <rtdbg.h>
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#include <stdint.h>
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#include <rtdevice.h>
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#include <rthw.h>
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#include "NuMicro.h"
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enum
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{
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EPWM_START = -1,
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#if defined(BSP_USING_EPWM0)
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EPWM0_IDX,
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#endif
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#if defined(BSP_USING_EPWM1)
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EPWM1_IDX,
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#endif
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EPWM_CNT
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};
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struct nu_epwm
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{
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struct rt_device_pwm dev;
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char *name;
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EPWM_T *epwm_base;
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};
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typedef struct nu_epwm *nu_epwm_t;
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static struct nu_epwm nu_epwm_arr [] =
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{
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#if defined(BSP_USING_EPWM0)
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{
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.name = "epwm0",
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.epwm_base = EPWM0,
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},
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#endif
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#if defined(BSP_USING_EPWM1)
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{
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.name = "epwm1",
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.epwm_base = EPWM1,
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},
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#endif
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{0}
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}; /* epwm nu_epwm */
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static rt_err_t nu_epwm_control(struct rt_device_pwm *device, int cmd, void *arg);
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static struct rt_pwm_ops nu_epwm_ops =
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{
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.control = nu_epwm_control
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};
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static rt_err_t nu_epwm_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable)
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{
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rt_err_t result = RT_EOK;
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EPWM_T *pwm_base = ((nu_epwm_t)device)->epwm_base;
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rt_uint32_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel;
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if (enable == RT_TRUE)
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{
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EPWM_EnableOutput(pwm_base, 1 << pwm_channel);
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EPWM_Start(pwm_base, 1 << pwm_channel);
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}
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else
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{
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EPWM_DisableOutput(pwm_base, 1 << pwm_channel);
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EPWM_ForceStop(pwm_base, 1 << pwm_channel);
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}
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return result;
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}
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static rt_err_t nu_epwm_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
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{
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if ((((struct rt_pwm_configuration *)configuration)->period) <= 0)
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return -(RT_ERROR);
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rt_uint8_t pwm_channel_pair;
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rt_uint32_t pwm_freq, pwm_dutycycle ;
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EPWM_T *pwm_base = ((nu_epwm_t)device)->epwm_base;
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rt_uint8_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel;
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rt_uint32_t pwm_period = ((struct rt_pwm_configuration *)configuration)->period;
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rt_uint32_t pwm_pulse = ((struct rt_pwm_configuration *)configuration)->pulse;
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rt_uint32_t pre_pwm_prescaler = EPWM_GET_PRESCALER(pwm_base, pwm_channel);
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if ((pwm_channel % 2) == 0)
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pwm_channel_pair = pwm_channel + 1;
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else
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pwm_channel_pair = pwm_channel - 1;
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pwm_freq = 1000000000 / pwm_period;
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pwm_dutycycle = (pwm_pulse * 100) / pwm_period;
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EPWM_ConfigOutputChannel(pwm_base, pwm_channel, pwm_freq, pwm_dutycycle) ;
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if ((pre_pwm_prescaler != 0) || (EPWM_GET_CNR(pwm_base, pwm_channel_pair) != 0) || (EPWM_GET_CMR(pwm_base, pwm_channel_pair) != 0))
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{
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if (pre_pwm_prescaler < EPWM_GET_PRESCALER(pwm_base, pwm_channel))
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{
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EPWM_SET_CNR(pwm_base, pwm_channel_pair, ((EPWM_GET_CNR(pwm_base, pwm_channel_pair) + 1) * (pre_pwm_prescaler + 1)) / (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1));
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EPWM_SET_CMR(pwm_base, pwm_channel_pair, (EPWM_GET_CMR(pwm_base, pwm_channel_pair) * (pre_pwm_prescaler + 1)) / (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1));
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}
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else if (pre_pwm_prescaler > EPWM_GET_PRESCALER(pwm_base, pwm_channel))
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{
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EPWM_SET_CNR(pwm_base, pwm_channel, ((EPWM_GET_CNR(pwm_base, pwm_channel) + 1) * (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)) / (pre_pwm_prescaler + 1));
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EPWM_SET_CMR(pwm_base, pwm_channel, (EPWM_GET_CMR(pwm_base, pwm_channel) * (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)) / (pre_pwm_prescaler + 1));
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}
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}
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return RT_EOK;
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}
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static rt_uint32_t nu_epwm_clksr(struct rt_device_pwm *device)
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{
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rt_uint32_t u32Src, u32EPWMClockSrc;
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EPWM_T *pwm_base = ((nu_epwm_t)device)->epwm_base;
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if (pwm_base == EPWM0)
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{
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u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk;
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}
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else /* (epwm == EPWM1) */
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{
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u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk;
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}
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if (u32Src == 0U)
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{
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/* clock source is from PLL clock */
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u32EPWMClockSrc = CLK_GetPLLClockFreq();
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}
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else
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{
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/* clock source is from PCLK */
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SystemCoreClockUpdate();
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if (pwm_base == EPWM0)
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{
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u32EPWMClockSrc = CLK_GetPCLK0Freq();
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}
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else /* (epwm == EPWM1) */
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{
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u32EPWMClockSrc = CLK_GetPCLK1Freq();
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}
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}
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return u32EPWMClockSrc;
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}
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static rt_err_t nu_epwm_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
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{
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rt_uint32_t pwm_real_period, pwm_real_duty, time_tick, u32EPWMClockSrc ;
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EPWM_T *pwm_base = ((nu_epwm_t)device)->epwm_base;
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rt_uint32_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel;
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rt_uint32_t pwm_prescale = EPWM_GET_PRESCALER(pwm_base, pwm_channel);
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rt_uint32_t pwm_period = EPWM_GET_CNR(pwm_base, pwm_channel);
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rt_uint32_t pwm_pulse = EPWM_GET_CMR(pwm_base, pwm_channel);
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u32EPWMClockSrc = nu_epwm_clksr(device);
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time_tick = 1000000000000 / u32EPWMClockSrc;
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pwm_real_period = (((pwm_prescale + 1) * (pwm_period + 1)) * time_tick) / 1000;
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pwm_real_duty = (((pwm_prescale + 1) * pwm_pulse * time_tick)) / 1000;
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((struct rt_pwm_configuration *)configuration)->period = pwm_real_period;
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((struct rt_pwm_configuration *)configuration)->pulse = pwm_real_duty;
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LOG_I("%s %d %d %d\n", ((nu_epwm_t)device)->name, configuration->channel, configuration->period, configuration->pulse);
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return RT_EOK;
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}
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static rt_err_t nu_epwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(configuration != RT_NULL);
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if (((((struct rt_pwm_configuration *)configuration)->channel) + 1) > EPWM_CHANNEL_NUM)
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return -(RT_ERROR);
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switch (cmd)
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{
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case PWM_CMD_ENABLE:
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return nu_epwm_enable(device, configuration, RT_TRUE);
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case PWM_CMD_DISABLE:
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return nu_epwm_enable(device, configuration, RT_FALSE);
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case PWM_CMD_SET:
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return nu_epwm_set(device, configuration);
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case PWM_CMD_GET:
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return nu_epwm_get(device, configuration);
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}
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return -(RT_EINVAL);
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}
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int rt_hw_epwm_init(void)
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{
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rt_err_t ret;
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int i;
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for (i = (EPWM_START + 1); i < EPWM_CNT; i++)
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{
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ret = rt_device_pwm_register(&nu_epwm_arr[i].dev, nu_epwm_arr[i].name, &nu_epwm_ops, RT_NULL);
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RT_ASSERT(ret == RT_EOK);
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}
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return 0;
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}
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INIT_DEVICE_EXPORT(rt_hw_epwm_init);
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#endif
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