2022-05-06 09:28:21 +08:00
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/*
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2022-05-31 11:53:56 +08:00
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* Copyright (c) 2006-2022, RT-Thread Development Team
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* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
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2022-05-06 09:28:21 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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2022-06-08 12:10:58 +08:00
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* Date Author Notes
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* 2022-04-28 CDT first version
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* 2022-06-07 xiaoxiaolisunny add hc32f460 series
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2022-06-15 10:37:27 +08:00
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* 2022-06-08 CDT fix a bug of RT_CAN_CMD_SET_FILTER
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2022-06-21 11:12:35 +08:00
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* 2022-06-15 lianghongquan fix bug, FILTER_COUNT, RT_CAN_CMD_SET_FILTER, interrupt setup and processing.
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2022-05-06 09:28:21 +08:00
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*/
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#include "drv_can.h"
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#include <drv_config.h>
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#include <board_config.h>
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#ifdef BSP_USING_CAN
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#define LOG_TAG "drv_can"
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#if !defined(BSP_USING_CAN1) && !defined(BSP_USING_CAN2)
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#error "Please define at least one BSP_USING_CANx"
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#endif
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#if defined (HC32F4A0)
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2022-05-15 20:57:35 +08:00
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#define FILTER_COUNT (16)
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#define CAN1_INT_SRC (INT_SRC_CAN1_HOST)
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#define CAN2_INT_SRC (INT_SRC_CAN2_HOST)
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2022-05-06 09:28:21 +08:00
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#endif
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2022-06-08 12:10:58 +08:00
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#if defined (HC32F460)
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2022-06-21 11:12:35 +08:00
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#define FILTER_COUNT (8)
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2022-06-08 12:10:58 +08:00
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#define CAN1_INT_SRC (INT_SRC_CAN_INT)
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#endif
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2022-05-06 09:28:21 +08:00
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enum
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{
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#ifdef BSP_USING_CAN1
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CAN1_INDEX,
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#endif
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#ifdef BSP_USING_CAN2
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CAN2_INDEX,
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#endif
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CAN_INDEX_MAX,
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};
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2022-05-15 20:57:35 +08:00
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struct can_baud_rate_tab
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2022-05-06 09:28:21 +08:00
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{
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rt_uint32_t baud_rate;
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stc_can_bit_time_config_t ll_sbt;
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};
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2022-05-15 20:57:35 +08:00
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static const struct can_baud_rate_tab g_baudrate_tab[] =
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2022-05-06 09:28:21 +08:00
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{
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2022-05-15 20:57:35 +08:00
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{CAN1MBaud, CAN_BIT_TIME_CONFIG_1M_BAUD},
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{CAN800kBaud, CAN_BIT_TIME_CONFIG_800K_BAUD},
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{CAN500kBaud, CAN_BIT_TIME_CONFIG_500K_BAUD},
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{CAN250kBaud, CAN_BIT_TIME_CONFIG_250K_BAUD},
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{CAN125kBaud, CAN_BIT_TIME_CONFIG_125K_BAUD},
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{CAN100kBaud, CAN_BIT_TIME_CONFIG_100K_BAUD},
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{CAN50kBaud, CAN_BIT_TIME_CONFIG_50K_BAUD},
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{CAN20kBaud, CAN_BIT_TIME_CONFIG_20K_BAUD},
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{CAN10kBaud, CAN_BIT_TIME_CONFIG_10K_BAUD},
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2022-05-06 09:28:21 +08:00
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};
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typedef struct
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{
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struct rt_can_device rt_can;
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2022-05-15 20:57:35 +08:00
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struct can_dev_init_params init;
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2022-05-06 09:28:21 +08:00
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CM_CAN_TypeDef *instance;
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stc_can_init_t ll_init;
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2022-05-15 20:57:35 +08:00
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} can_device;
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2022-05-06 09:28:21 +08:00
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2022-05-15 20:57:35 +08:00
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static can_device g_can_dev_array[] =
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2022-05-06 09:28:21 +08:00
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{
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2022-06-08 12:10:58 +08:00
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#if defined (HC32F4A0)
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2022-05-06 09:28:21 +08:00
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#ifdef BSP_USING_CAN1
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{
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{0},
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2022-05-15 20:57:35 +08:00
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CAN1_INIT_PARAMS,
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2022-05-06 09:28:21 +08:00
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.instance = CM_CAN1,
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},
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#endif
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#ifdef BSP_USING_CAN2
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{
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{0},
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2022-05-15 20:57:35 +08:00
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CAN2_INIT_PARAMS,
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2022-05-06 09:28:21 +08:00
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.instance = CM_CAN2,
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},
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#endif
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2022-06-08 12:10:58 +08:00
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#endif
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#if defined (HC32F460)
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#ifdef BSP_USING_CAN1
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{
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{0},
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CAN1_INIT_PARAMS,
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.instance = CM_CAN,
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},
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#endif
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#endif
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2022-05-06 09:28:21 +08:00
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};
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2022-05-15 20:57:35 +08:00
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static rt_uint32_t _get_can_baud_index(rt_uint32_t baud)
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2022-05-06 09:28:21 +08:00
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{
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rt_uint32_t len, index;
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2022-05-15 20:57:35 +08:00
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len = sizeof(g_baudrate_tab) / sizeof(g_baudrate_tab[0]);
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2022-05-06 09:28:21 +08:00
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for (index = 0; index < len; index++)
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{
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2022-05-15 20:57:35 +08:00
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if (g_baudrate_tab[index].baud_rate == baud)
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2022-05-06 09:28:21 +08:00
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return index;
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}
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return 0; /* default baud is CAN1MBaud */
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}
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2022-05-15 20:57:35 +08:00
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static rt_uint32_t _get_can_work_mode(rt_uint32_t mode)
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2022-05-06 09:28:21 +08:00
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{
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rt_uint32_t work_mode;
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switch (mode)
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{
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case RT_CAN_MODE_NORMAL:
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work_mode = CAN_WORK_MD_NORMAL;
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break;
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2022-08-14 10:59:28 +08:00
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case RT_CAN_MODE_LISTEN:
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2022-05-06 09:28:21 +08:00
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work_mode = CAN_WORK_MD_SILENT;
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break;
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case RT_CAN_MODE_LOOPBACK:
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work_mode = CAN_WORK_MD_ELB;
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break;
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2022-08-14 10:59:28 +08:00
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case RT_CAN_MODE_LOOPBACKANLISTEN:
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2022-05-06 09:28:21 +08:00
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work_mode = CAN_WORK_MD_ELB_SILENT;
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break;
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default:
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work_mode = CAN_WORK_MD_NORMAL;
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break;
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}
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return work_mode;
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}
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static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg)
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{
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rt_uint32_t baud_index;
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2022-05-15 20:57:35 +08:00
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can_device *p_can_dev;
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2022-05-06 09:28:21 +08:00
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rt_err_t rt_ret = RT_EOK;
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RT_ASSERT(can);
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RT_ASSERT(cfg);
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2022-05-15 20:57:35 +08:00
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p_can_dev = (can_device *)rt_container_of(can, can_device, rt_can);
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RT_ASSERT(p_can_dev);
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2022-05-06 09:28:21 +08:00
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2022-05-15 20:57:35 +08:00
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p_can_dev->ll_init.u8WorkMode = _get_can_work_mode(cfg->mode);
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baud_index = _get_can_baud_index(cfg->baud_rate);
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p_can_dev->ll_init.stcBitCfg = g_baudrate_tab[baud_index].ll_sbt;
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2022-05-06 09:28:21 +08:00
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/* init can */
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2022-05-15 20:57:35 +08:00
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int32_t ret = CAN_Init(p_can_dev->instance, &p_can_dev->ll_init);
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2022-05-06 09:28:21 +08:00
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if (ret != LL_OK)
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{
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2023-03-16 12:44:05 +08:00
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rt_ret = -RT_EINVAL;
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2022-05-06 09:28:21 +08:00
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}
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return rt_ret;
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}
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2022-05-15 20:57:35 +08:00
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static uint16_t _get_filter_idx(struct rt_can_filter_config *filter_cfg)
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2022-05-06 09:28:21 +08:00
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{
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uint16_t u16FilterSelected = 0;
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for (int i = 0; i < filter_cfg->count; i++)
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{
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2022-11-22 10:45:51 +08:00
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if (filter_cfg->items[i].hdr_bank != -1)
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2022-05-06 09:28:21 +08:00
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{
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2022-11-22 10:45:51 +08:00
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u16FilterSelected |= 1 << filter_cfg->items[i].hdr_bank;
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2022-05-06 09:28:21 +08:00
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}
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}
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for (int i = 0; i < filter_cfg->count; i++)
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{
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2022-11-22 10:45:51 +08:00
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if (filter_cfg->items[i].hdr_bank == -1)
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2022-05-06 09:28:21 +08:00
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{
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for (int j = 0; j < FILTER_COUNT; j++)
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{
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if ((u16FilterSelected & 1 << j) == 0)
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{
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2022-11-22 10:45:51 +08:00
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filter_cfg->items[i].hdr_bank = j;
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u16FilterSelected |= 1 << filter_cfg->items[i].hdr_bank;
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2022-05-06 09:28:21 +08:00
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break;
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}
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}
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}
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}
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return u16FilterSelected;
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}
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static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
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{
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2022-05-15 20:57:35 +08:00
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can_device *p_can_dev;
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2022-05-06 09:28:21 +08:00
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rt_uint32_t argval;
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struct rt_can_filter_config *filter_cfg;
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RT_ASSERT(can != RT_NULL);
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2022-05-15 20:57:35 +08:00
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p_can_dev = (can_device *)rt_container_of(can, can_device, rt_can);
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RT_ASSERT(p_can_dev);
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2022-05-06 09:28:21 +08:00
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switch (cmd)
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{
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case RT_DEVICE_CTRL_CLR_INT:
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argval = (rt_uint32_t) arg;
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switch (argval)
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{
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case RT_DEVICE_FLAG_INT_RX:
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2022-06-21 11:12:35 +08:00
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CAN_IntCmd(p_can_dev->instance, CAN_INT_RX, DISABLE);
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CAN_IntCmd(p_can_dev->instance, CAN_INT_RX_BUF_WARN, DISABLE);
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CAN_IntCmd(p_can_dev->instance, CAN_INT_RX_BUF_FULL, DISABLE);
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CAN_IntCmd(p_can_dev->instance, CAN_INT_RX_OVERRUN, DISABLE);
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2022-05-06 09:28:21 +08:00
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break;
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case RT_DEVICE_FLAG_INT_TX:
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2022-06-21 11:12:35 +08:00
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CAN_IntCmd(p_can_dev->instance, CAN_INT_STB_TX, DISABLE);
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CAN_IntCmd(p_can_dev->instance, CAN_INT_PTB_TX, DISABLE);
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2022-05-06 09:28:21 +08:00
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break;
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case RT_DEVICE_CAN_INT_ERR:
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2022-05-15 20:57:35 +08:00
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CAN_IntCmd(p_can_dev->instance, CAN_INT_ERR_INT, DISABLE);
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CAN_IntCmd(p_can_dev->instance, CAN_INT_ARBITR_LOST, DISABLE);
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CAN_IntCmd(p_can_dev->instance, CAN_INT_ERR_PASSIVE, DISABLE);
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CAN_IntCmd(p_can_dev->instance, CAN_INT_BUS_ERR, DISABLE);
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2022-05-06 09:28:21 +08:00
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break;
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default:
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break;
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}
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break;
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case RT_DEVICE_CTRL_SET_INT:
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argval = (rt_uint32_t) arg;
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switch (argval)
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{
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case RT_DEVICE_FLAG_INT_RX:
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2022-06-21 11:12:35 +08:00
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CAN_IntCmd(p_can_dev->instance, CAN_INT_RX, ENABLE);
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CAN_IntCmd(p_can_dev->instance, CAN_INT_RX_BUF_WARN, ENABLE);
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CAN_IntCmd(p_can_dev->instance, CAN_INT_RX_BUF_FULL, ENABLE);
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CAN_IntCmd(p_can_dev->instance, CAN_INT_RX_OVERRUN, ENABLE);
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2022-05-06 09:28:21 +08:00
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break;
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case RT_DEVICE_FLAG_INT_TX:
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2022-06-21 11:12:35 +08:00
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CAN_IntCmd(p_can_dev->instance, CAN_INT_STB_TX, ENABLE);
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CAN_IntCmd(p_can_dev->instance, CAN_INT_PTB_TX, ENABLE);
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2022-05-06 09:28:21 +08:00
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break;
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case RT_DEVICE_CAN_INT_ERR:
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2022-05-15 20:57:35 +08:00
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CAN_IntCmd(p_can_dev->instance, CAN_INT_ERR_INT, ENABLE);
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CAN_IntCmd(p_can_dev->instance, CAN_INT_ARBITR_LOST, ENABLE);
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CAN_IntCmd(p_can_dev->instance, CAN_INT_ERR_PASSIVE, ENABLE);
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CAN_IntCmd(p_can_dev->instance, CAN_INT_BUS_ERR, ENABLE);
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2022-05-06 09:28:21 +08:00
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break;
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default:
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break;
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}
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break;
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case RT_CAN_CMD_SET_FILTER:
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if (RT_NULL != arg)
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{
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filter_cfg = (struct rt_can_filter_config *)arg;
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if (filter_cfg->count == 0)
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{
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return -RT_EINVAL;
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}
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RT_ASSERT(filter_cfg->count <= FILTER_COUNT);
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/* get default filter */
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2022-05-15 20:57:35 +08:00
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if (p_can_dev->ll_init.pstcFilter)
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2022-05-06 09:28:21 +08:00
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{
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2022-05-15 20:57:35 +08:00
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p_can_dev->ll_init.u16FilterSelect = _get_filter_idx(filter_cfg);
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2022-05-06 09:28:21 +08:00
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for (int i = 0; i < filter_cfg->count; i++)
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{
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2022-06-21 11:12:35 +08:00
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p_can_dev->ll_init.pstcFilter[i].u32ID = filter_cfg->items[i].id & 0x1FFFFFFF;
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/* rt-thread CAN mask, 1 mean filer, 0 mean ignore. *
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* HDSC HC32 CAN mask, 0 mean filer, 1 mean ignore. */
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p_can_dev->ll_init.pstcFilter[i].u32IDMask = (~filter_cfg->items[i].mask) & 0x1FFFFFFF;
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switch (filter_cfg->items[i].ide)
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2022-06-15 10:37:27 +08:00
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{
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2022-06-21 11:12:35 +08:00
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case (RT_CAN_STDID):
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p_can_dev->ll_init.pstcFilter[i].u32IDType = CAN_ID_STD;
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break;
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case (RT_CAN_EXTID):
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p_can_dev->ll_init.pstcFilter[i].u32IDType = CAN_ID_EXT;
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break;
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default:
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|
|
p_can_dev->ll_init.pstcFilter[i].u32IDType = CAN_ID_STD_EXT;
|
|
|
|
break;
|
2022-06-15 10:37:27 +08:00
|
|
|
}
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
}
|
2022-05-15 20:57:35 +08:00
|
|
|
(void)CAN_Init(p_can_dev->instance, &p_can_dev->ll_init);
|
2022-05-06 09:28:21 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case RT_CAN_CMD_SET_MODE:
|
|
|
|
argval = (rt_uint32_t) arg;
|
|
|
|
if (argval != RT_CAN_MODE_NORMAL &&
|
2022-08-14 10:59:28 +08:00
|
|
|
argval != RT_CAN_MODE_LISTEN &&
|
2022-05-06 09:28:21 +08:00
|
|
|
argval != RT_CAN_MODE_LOOPBACK &&
|
2022-08-14 10:59:28 +08:00
|
|
|
argval != RT_CAN_MODE_LOOPBACKANLISTEN)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
|
|
|
return -RT_ERROR;
|
|
|
|
}
|
2022-05-15 20:57:35 +08:00
|
|
|
if (argval != p_can_dev->rt_can.config.mode)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
p_can_dev->rt_can.config.mode = argval;
|
|
|
|
_can_config(can, &p_can_dev->rt_can.config);
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case RT_CAN_CMD_SET_BAUD:
|
|
|
|
argval = (rt_uint32_t) arg;
|
|
|
|
if (argval != CAN1MBaud &&
|
|
|
|
argval != CAN800kBaud &&
|
|
|
|
argval != CAN500kBaud &&
|
|
|
|
argval != CAN250kBaud &&
|
|
|
|
argval != CAN125kBaud &&
|
|
|
|
argval != CAN100kBaud &&
|
|
|
|
argval != CAN50kBaud &&
|
|
|
|
argval != CAN20kBaud &&
|
|
|
|
argval != CAN10kBaud)
|
|
|
|
{
|
|
|
|
return -RT_ERROR;
|
|
|
|
}
|
2022-05-15 20:57:35 +08:00
|
|
|
if (argval != p_can_dev->rt_can.config.baud_rate)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
p_can_dev->rt_can.config.baud_rate = argval;
|
|
|
|
_can_config(can, &p_can_dev->rt_can.config);
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case RT_CAN_CMD_SET_PRIV:
|
|
|
|
argval = (rt_uint32_t) arg;
|
|
|
|
if (argval != RT_CAN_MODE_PRIV &&
|
|
|
|
argval != RT_CAN_MODE_NOPRIV)
|
|
|
|
{
|
|
|
|
return -RT_ERROR;
|
|
|
|
}
|
2022-05-15 20:57:35 +08:00
|
|
|
if (argval != p_can_dev->rt_can.config.privmode)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
p_can_dev->rt_can.config.privmode = argval;
|
|
|
|
return _can_config(can, &p_can_dev->rt_can.config);
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case RT_CAN_CMD_GET_STATUS:
|
|
|
|
{
|
|
|
|
struct rt_can_status *rt_can_stat = (struct rt_can_status *)arg;
|
|
|
|
stc_can_error_info_t stcErr = {0};
|
2022-05-15 20:57:35 +08:00
|
|
|
CAN_GetErrorInfo(p_can_dev->instance, &stcErr);
|
2022-05-06 09:28:21 +08:00
|
|
|
rt_can_stat->rcverrcnt = stcErr.u8RxErrorCount;
|
|
|
|
rt_can_stat->snderrcnt = stcErr.u8TxErrorCount;
|
|
|
|
rt_can_stat->lasterrtype = stcErr.u8ErrorType;
|
2022-05-15 20:57:35 +08:00
|
|
|
rt_can_stat->errcode = CAN_GetStatusValue(p_can_dev->instance);
|
2022-05-06 09:28:21 +08:00
|
|
|
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
|
|
|
|
}
|
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
|
|
|
|
{
|
|
|
|
struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
|
|
|
|
stc_can_tx_frame_t stc_tx_frame = {0};
|
|
|
|
int32_t ll_ret;
|
|
|
|
|
|
|
|
RT_ASSERT(can != RT_NULL);
|
2022-05-15 20:57:35 +08:00
|
|
|
can_device *p_can_dev = (can_device *)rt_container_of(can, can_device, rt_can);
|
|
|
|
RT_ASSERT(p_can_dev);
|
2022-05-06 09:28:21 +08:00
|
|
|
|
|
|
|
stc_tx_frame.u32ID = pmsg->id;
|
|
|
|
if (RT_CAN_DTR == pmsg->rtr)
|
|
|
|
{
|
|
|
|
stc_tx_frame.RTR = 0;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
stc_tx_frame.RTR = 1;
|
|
|
|
}
|
|
|
|
/* Set up the DLC */
|
|
|
|
stc_tx_frame.DLC = pmsg->len & 0x0FU;
|
2022-06-08 12:10:58 +08:00
|
|
|
/* Set up the IDE */
|
|
|
|
stc_tx_frame.IDE = pmsg->ide;
|
2022-05-06 09:28:21 +08:00
|
|
|
/* Set up the data field */
|
|
|
|
rt_memcpy(&stc_tx_frame.au8Data, pmsg->data, sizeof(stc_tx_frame.au8Data));
|
2022-05-15 20:57:35 +08:00
|
|
|
ll_ret = CAN_FillTxFrame(p_can_dev->instance, CAN_TX_BUF_PTB, &stc_tx_frame);
|
2022-05-06 09:28:21 +08:00
|
|
|
if (ll_ret != LL_OK)
|
|
|
|
{
|
|
|
|
return RT_ERROR;
|
|
|
|
}
|
|
|
|
/* Request transmission */
|
2022-05-15 20:57:35 +08:00
|
|
|
CAN_StartTx(p_can_dev->instance, CAN_TX_REQ_PTB);
|
|
|
|
|
2022-05-06 09:28:21 +08:00
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
|
|
|
|
{
|
|
|
|
int32_t ll_ret;
|
|
|
|
struct rt_can_msg *pmsg;
|
|
|
|
stc_can_rx_frame_t ll_rx_frame;
|
|
|
|
|
|
|
|
RT_ASSERT(can != RT_NULL);
|
2022-05-15 20:57:35 +08:00
|
|
|
can_device *p_can_dev = (can_device *)rt_container_of(can, can_device, rt_can);
|
|
|
|
RT_ASSERT(p_can_dev);
|
2022-05-06 09:28:21 +08:00
|
|
|
|
|
|
|
pmsg = (struct rt_can_msg *) buf;
|
|
|
|
/* get data */
|
2022-05-15 20:57:35 +08:00
|
|
|
ll_ret = CAN_GetRxFrame(p_can_dev->instance, &ll_rx_frame);
|
2022-05-06 09:28:21 +08:00
|
|
|
if (ll_ret != LL_OK)
|
|
|
|
return -RT_ERROR;
|
2022-05-15 20:57:35 +08:00
|
|
|
|
2022-05-06 09:28:21 +08:00
|
|
|
/* get id */
|
2022-06-08 12:10:58 +08:00
|
|
|
if (0 == ll_rx_frame.IDE)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
|
|
|
pmsg->ide = RT_CAN_STDID;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
pmsg->ide = RT_CAN_EXTID;
|
|
|
|
}
|
|
|
|
pmsg->id = ll_rx_frame.u32ID;
|
|
|
|
/* get type */
|
|
|
|
if (0 == ll_rx_frame.RTR)
|
|
|
|
{
|
|
|
|
pmsg->rtr = RT_CAN_DTR;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
pmsg->rtr = RT_CAN_RTR;
|
|
|
|
}
|
|
|
|
/* get len */
|
|
|
|
pmsg->len = ll_rx_frame.DLC;
|
2022-11-22 10:45:51 +08:00
|
|
|
/* get hdr_index */
|
|
|
|
pmsg->hdr_index = 0;
|
2022-05-06 09:28:21 +08:00
|
|
|
rt_memcpy(pmsg->data, &ll_rx_frame.au8Data, ll_rx_frame.DLC);
|
|
|
|
|
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct rt_can_ops _can_ops =
|
|
|
|
{
|
|
|
|
_can_config,
|
|
|
|
_can_control,
|
|
|
|
_can_sendmsg,
|
|
|
|
_can_recvmsg,
|
|
|
|
};
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
static void _can_isr(can_device *p_can_dev)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
|
|
|
stc_can_error_info_t stcErr;
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
(void)CAN_GetErrorInfo(p_can_dev->instance, &stcErr);
|
2022-05-06 09:28:21 +08:00
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_BUS_OFF) == SET)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
/* BUS OFF. */
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
2022-06-21 11:12:35 +08:00
|
|
|
if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_ERR_INT) == SET)
|
|
|
|
{
|
|
|
|
/* ERROR. */
|
|
|
|
CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_ERR_INT);
|
|
|
|
}
|
|
|
|
if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_BUS_ERR) == SET)
|
|
|
|
{
|
|
|
|
/* BUS ERROR. */
|
|
|
|
CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_BUS_ERR);
|
|
|
|
}
|
|
|
|
if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_ERR_PASSIVE) == SET)
|
|
|
|
{
|
|
|
|
/* error-passive to error-active or error-active to error-passive. */
|
|
|
|
CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_ERR_PASSIVE);
|
|
|
|
}
|
2022-05-06 09:28:21 +08:00
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_RX_BUF_OVF) == SET)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
/* RX overflow. */
|
|
|
|
rt_hw_can_isr(&p_can_dev->rt_can, RT_CAN_EVENT_RXOF_IND);
|
|
|
|
CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_RX_BUF_OVF);
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_TX_BUF_FULL) == SET)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
/* TX buffer full. */
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_TX_ABORTED) == SET)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
/* TX aborted. */
|
|
|
|
CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_TX_ABORTED);
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_ARBITR_LOST) == SET)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
rt_hw_can_isr(&p_can_dev->rt_can, RT_CAN_EVENT_TX_FAIL);
|
|
|
|
CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_ARBITR_LOST);
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_STB_TX) == SET)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
/* STB transmitted. */
|
|
|
|
CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_STB_TX);
|
|
|
|
rt_hw_can_isr(&p_can_dev->rt_can, RT_CAN_EVENT_TX_DONE);
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_PTB_TX) == SET)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
/* PTB transmitted. */
|
|
|
|
CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_PTB_TX);
|
|
|
|
rt_hw_can_isr(&p_can_dev->rt_can, RT_CAN_EVENT_TX_DONE);
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_RX) == SET)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
/* Received a frame. */
|
|
|
|
CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_RX);
|
|
|
|
rt_hw_can_isr(&p_can_dev->rt_can, RT_CAN_EVENT_RX_IND);
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_RX_BUF_WARN) == SET)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
/* RX buffer warning. */
|
|
|
|
CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_RX_BUF_WARN);
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_RX_BUF_FULL) == SET)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
/* RX buffer full. */
|
|
|
|
CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_RX_BUF_FULL);
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_RX_OVERRUN) == SET)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
/* RX buffer overrun. */
|
|
|
|
CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_RX_OVERRUN);
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_TEC_REC_WARN) == SET)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
/* TEC or REC reached warning limit. */
|
|
|
|
CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_TEC_REC_WARN);
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
if (CAN_TTC_GetStatus(p_can_dev->instance, CAN_TTC_FLAG_TIME_TRIG) == SET)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
/* Time trigger interrupt. */
|
|
|
|
CAN_TTC_ClearStatus(p_can_dev->instance, CAN_TTC_FLAG_TIME_TRIG);
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
if (CAN_TTC_GetStatus(p_can_dev->instance, CAN_TTC_FLAG_TRIG_ERR) == SET)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
/* Trigger error interrupt. */
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
if (CAN_TTC_GetStatus(p_can_dev->instance, CAN_TTC_FLAG_WATCH_TRIG) == SET)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
/* Watch trigger interrupt. */
|
|
|
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CAN_TTC_ClearStatus(p_can_dev->instance, CAN_TTC_FLAG_WATCH_TRIG);
|
2022-05-06 09:28:21 +08:00
|
|
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}
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|
|
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}
|
|
|
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#if defined(BSP_USING_CAN1)
|
2022-05-15 20:57:35 +08:00
|
|
|
static void _can1_irq_handler(void)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
|
|
|
rt_interrupt_enter();
|
2022-05-15 20:57:35 +08:00
|
|
|
_can_isr(&g_can_dev_array[CAN1_INDEX]);
|
2022-05-06 09:28:21 +08:00
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if defined(BSP_USING_CAN2)
|
2022-05-15 20:57:35 +08:00
|
|
|
static void _can2_irq_handler(void)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
|
|
|
rt_interrupt_enter();
|
2022-05-15 20:57:35 +08:00
|
|
|
_can_isr(&g_can_dev_array[CAN2_INDEX]);
|
2022-05-06 09:28:21 +08:00
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
static void _can_clock_enable(void)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
#if defined(HC32F4A0)
|
|
|
|
#if defined(BSP_USING_CAN1)
|
|
|
|
FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN1, ENABLE);
|
|
|
|
#endif
|
|
|
|
#if defined(BSP_USING_CAN2)
|
|
|
|
FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN2, ENABLE);
|
2022-05-06 09:28:21 +08:00
|
|
|
#endif
|
2022-05-15 20:57:35 +08:00
|
|
|
#endif
|
2022-06-08 12:10:58 +08:00
|
|
|
|
|
|
|
#if defined(HC32F460)
|
|
|
|
#if defined(BSP_USING_CAN1)
|
|
|
|
FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN, ENABLE);
|
|
|
|
#endif
|
|
|
|
#endif
|
2022-05-15 20:57:35 +08:00
|
|
|
}
|
2022-05-06 09:28:21 +08:00
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
static void _can_irq_config(void)
|
|
|
|
{
|
2022-05-06 09:28:21 +08:00
|
|
|
struct hc32_irq_config irq_config;
|
|
|
|
#if defined(BSP_USING_CAN1)
|
2022-05-15 20:57:35 +08:00
|
|
|
irq_config.irq_num = BSP_CAN1_IRQ_NUM;
|
2022-05-06 09:28:21 +08:00
|
|
|
irq_config.int_src = CAN1_INT_SRC;
|
2022-05-15 20:57:35 +08:00
|
|
|
irq_config.irq_prio = BSP_CAN1_IRQ_PRIO;
|
2022-05-06 09:28:21 +08:00
|
|
|
/* register interrupt */
|
|
|
|
hc32_install_irq_handler(&irq_config,
|
2022-05-15 20:57:35 +08:00
|
|
|
_can1_irq_handler,
|
2022-05-06 09:28:21 +08:00
|
|
|
RT_TRUE);
|
|
|
|
#endif
|
|
|
|
#if defined(BSP_USING_CAN2)
|
2022-05-15 20:57:35 +08:00
|
|
|
irq_config.irq_num = BSP_CAN2_IRQ_NUM;
|
2022-05-06 09:28:21 +08:00
|
|
|
irq_config.int_src = CAN2_INT_SRC;
|
2022-05-15 20:57:35 +08:00
|
|
|
irq_config.irq_prio = BSP_CAN2_IRQ_PRIO;
|
2022-05-06 09:28:21 +08:00
|
|
|
/* register interrupt */
|
|
|
|
hc32_install_irq_handler(&irq_config,
|
2022-05-15 20:57:35 +08:00
|
|
|
_can2_irq_handler,
|
2022-05-06 09:28:21 +08:00
|
|
|
RT_TRUE);
|
|
|
|
#endif
|
2022-05-15 20:57:35 +08:00
|
|
|
}
|
2022-05-06 09:28:21 +08:00
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
extern rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx);
|
|
|
|
extern void CanPhyEnable(void);
|
|
|
|
int rt_hw_can_init(void)
|
|
|
|
{
|
|
|
|
struct can_configure rt_can_config = CANDEFAULTCONFIG;
|
|
|
|
rt_can_config.privmode = RT_CAN_MODE_NOPRIV;
|
|
|
|
rt_can_config.ticks = 50;
|
|
|
|
#ifdef RT_CAN_USING_HDR
|
|
|
|
rt_can_config.maxhdr = FILTER_COUNT;
|
2022-05-06 09:28:21 +08:00
|
|
|
#endif
|
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
_can_irq_config();
|
|
|
|
_can_clock_enable();
|
2022-05-06 09:28:21 +08:00
|
|
|
CanPhyEnable();
|
|
|
|
int result = RT_EOK;
|
|
|
|
uint32_t i = 0;
|
|
|
|
for (; i < CAN_INDEX_MAX; i++)
|
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
CAN_StructInit(&g_can_dev_array[i].ll_init);
|
|
|
|
if (g_can_dev_array[i].ll_init.pstcFilter == RT_NULL)
|
2022-05-06 09:28:21 +08:00
|
|
|
{
|
2022-05-15 20:57:35 +08:00
|
|
|
g_can_dev_array[i].ll_init.pstcFilter = (stc_can_filter_config_t *)rt_malloc(sizeof(stc_can_filter_config_t) * FILTER_COUNT);
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
2022-05-15 20:57:35 +08:00
|
|
|
RT_ASSERT((g_can_dev_array[i].ll_init.pstcFilter != RT_NULL));
|
2022-05-06 09:28:21 +08:00
|
|
|
|
2022-05-15 20:57:35 +08:00
|
|
|
rt_memset(g_can_dev_array[i].ll_init.pstcFilter, 0, sizeof(stc_can_filter_config_t) * FILTER_COUNT);
|
|
|
|
g_can_dev_array[i].ll_init.pstcFilter[0].u32ID = 0U;
|
|
|
|
g_can_dev_array[i].ll_init.pstcFilter[0].u32IDMask = 0x1FFFFFFF;
|
2022-06-08 12:10:58 +08:00
|
|
|
g_can_dev_array[i].ll_init.pstcFilter[0].u32IDType = CAN_ID_STD_EXT;
|
2022-05-15 20:57:35 +08:00
|
|
|
g_can_dev_array[i].ll_init.u16FilterSelect = CAN_FILTER1;
|
|
|
|
g_can_dev_array[i].rt_can.config = rt_can_config;
|
2022-05-06 09:28:21 +08:00
|
|
|
|
2022-06-15 10:37:27 +08:00
|
|
|
/* register CAN device */
|
2022-05-15 20:57:35 +08:00
|
|
|
rt_hw_board_can_init(g_can_dev_array[i].instance);
|
|
|
|
rt_hw_can_register(&g_can_dev_array[i].rt_can,
|
|
|
|
g_can_dev_array[i].init.name,
|
2022-05-06 09:28:21 +08:00
|
|
|
&_can_ops,
|
2022-05-15 20:57:35 +08:00
|
|
|
&g_can_dev_array[i]);
|
2022-05-06 09:28:21 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
INIT_DEVICE_EXPORT(rt_hw_can_init);
|
|
|
|
|
|
|
|
#endif /* BSP_USING_CAN */
|
|
|
|
|
|
|
|
/************************** end of file ******************/
|