352 lines
18 KiB
C
352 lines
18 KiB
C
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////////////////////////////////////////////////////////////////////////////////
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/// @file hal_spi.h
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/// @author AE TEAM
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/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SPI
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/// FIRMWARE LIBRARY.
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////////////////////////////////////////////////////////////////////////////////
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/// @attention
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///
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/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
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/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
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/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
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/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
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/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
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/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
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///
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/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
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////////////////////////////////////////////////////////////////////////////////
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// Define to prevent recursive inclusion
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#ifndef __HAL_SPI_H
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#define __HAL_SPI_H
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// Files includes
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#include "types.h"
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#include "reg_spi.h"
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////////////////////////////////////////////////////////////////////////////////
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/// @addtogroup MM32_Hardware_Abstract_Layer
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup SPI_HAL
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/// @brief SPI HAL modules
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup SPI_Exported_Types
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SPI mode enum definition
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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SPI_Mode_Slave = 0x0000, ///< SPI slave mode
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SPI_Mode_Master = SPI_GCR_MODE ///< SPI master mode
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} SPI_Mode_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SPI data size enum definition
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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SPI_DataSize_8b = 0x0000, ///< 8 bits valid data
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SPI_DataSize_32b = SPI_GCR_DWSEL ///< 32 bits valid data
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} SPI_DataSize_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SPI clock polarity enum definition
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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SPI_CPOL_Low = 0x0000, ///< The clock is low in idle state.
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SPI_CPOL_High = SPI_CCR_CPOL ///< The clock is high in idle state.
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} SPI_CPOL_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SPI clock phase enum definition
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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SPI_CPHA_2Edge = 0x0000, ///< Data sampling starts from the second clock edge.
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SPI_CPHA_1Edge = SPI_CCR_CPHA ///< Data sampling starts from the first clock edge.
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} SPI_CPHA_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SPI nss control mode enum definition
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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SPI_NSS_Soft = 0x0000,
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SPI_NSS_Hard = SPI_GCR_NSS
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} SPI_NSS_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SPI baud rate prescaler enum definition
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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SPI_BaudRatePrescaler_2 = 0x0002, ///< SCK clock devide by 2
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SPI_BaudRatePrescaler_4 = 0x0004, ///< SCK clock devide by 4
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SPI_BaudRatePrescaler_8 = 0x0008, ///< SCK clock devide by 7
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SPI_BaudRatePrescaler_16 = 0x0010, ///< SCK clock devide by 16
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SPI_BaudRatePrescaler_32 = 0x0020, ///< SCK clock devide by 32
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SPI_BaudRatePrescaler_64 = 0x0040, ///< SCK clock devide by 64
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SPI_BaudRatePrescaler_128 = 0x0080, ///< SCK clock devide by 128
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SPI_BaudRatePrescaler_256 = 0x0100 ///< SCK clock devide by 256
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} SPI_BaudRatePrescaler_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SPI first bit enum definition
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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SPI_FirstBit_MSB = 0x0000, ///< Data transfers start from MSB
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SPI_FirstBit_LSB = SPI_CCR_LSBFE ///< Data transfers start from LSB
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} SPI_FirstBit_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SPI FIFO trigger level enum definition
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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SPI_RXTLF = SPI_GCR_RXTLF_Half, ///< RX FIFO trigger level
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SPI_TXTLF = SPI_GCR_TXTLF_Half ///< TX FIFO trigger level
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} SPI_TLF_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SPI bit derection enum definition
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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SPI_Direction_Rx, ///< Receive enable
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SPI_Direction_Tx, ///< Transmit enable
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SPI_Disable_Rx, ///< Receive disable
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SPI_Disable_Tx ///< Transmit disable
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} SPI_Direction_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SPI flag enum definition
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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SPI_FLAG_RXAVL = SPI_SR_RXAVL, ///< Receive 1 byte available data flag
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SPI_FLAG_TXEPT = SPI_SR_TXEPT, ///< Transmitter empty flag
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SPI_FLAG_TXFULL = SPI_SR_TXFULL, ///< Transmitter FIFO full status flag
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SPI_FLAG_RXAVL_4BYTE = SPI_SR_RXAVL_4BYTE ///< Receive 4 bytes available data flag
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} SPI_FLAG_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SPI slave mode data edge adjust enum definition
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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SPI_SlaveAdjust_LOW, ///< SPI slave mode data edge adjust in low speed mode
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SPI_SlaveAdjust_FAST ///< SPI slave mode data edge adjust in fast speed mode
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} SPI_SlaveAdjust_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SPI data edge adjust enum definition
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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SPI_DataEdgeAdjust_LOW, ///< SPI data edge adjust in low speed mode
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SPI_DataEdgeAdjust_FAST ///< SPI data edge adjust in fast speed mode
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} SPI_DataEdgeAdjust_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SPI interruput enum definition
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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SPI_IT_TXEPT = 0x40, ///< Transmitter empty interrupt
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SPI_IT_RXFULL = 0x20, ///< RX FIFO full interrupt
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SPI_IT_RXMATCH = 0x10, ///< Receive data match the RXDNR number interrut
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SPI_IT_RXOERR = 0x08, ///< Receive overrun error interrupt
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SPI_IT_UNDERRUN = 0x04, ///< Underrun interrupt
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SPI_IT_RX = 0x02, ///< Receive available data interrupt
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SPI_IT_TX = 0x01 ///< Transmit FIFO available interrupt
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} SPI_IT_TypeDef;
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typedef enum {
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I2S_Standard_Phillips = 0x0000,
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I2S_Standard_MSB = 0x0010,
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I2S_Standard_LSB = 0x0020,
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I2S_Standard_PCMShort = 0x0030,
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I2S_Standard_PCMLong = 0x00B0,
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} SPI_I2S_STANDARD_TypeDef;
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typedef enum {
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I2S_DataFormat_16b = 0x0000,
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I2S_DataFormat_16bextended = 0x0001,
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I2S_DataFormat_24b = 0x0003,
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I2S_DataFormat_32b = 0x0005,
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} SPI_I2S_DATAFORMAT_TypeDef;
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typedef enum {
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I2S_AudioFreq_192k = (192000),
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I2S_AudioFreq_96k = (96000),
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I2S_AudioFreq_48k = (48000),
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I2S_AudioFreq_44k = (44100),
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I2S_AudioFreq_32k = (32000),
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I2S_AudioFreq_24k = (24000),
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I2S_AudioFreq_22k = (22050),
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I2S_AudioFreq_16k = (16000),
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I2S_AudioFreq_11k = (11025),
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I2S_AudioFreq_12k = (12000),
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I2S_AudioFreq_8k = (8000),
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I2S_AudioFreq_4k = (4000),
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I2S_AudioFreq_Default = (2),
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} SPI_I2S_AUDIO_FREQ_TypeDef;
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typedef enum {
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I2S_Mode_SlaveTx = 0x0000,
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I2S_Mode_SlaveRx = 0x0100,
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I2S_Mode_MasterTx = 0x0200,
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I2S_Mode_MasterRx = 0x0300,
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} SPI_I2S_TRANS_MODE_TypeDef;
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typedef enum {
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I2S_MCLKOutput_Enable = 0x0800,
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I2S_MCLKOutput_Disable = 0x0000,
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} SPI_I2S_MCLK_OUTPUT_TypeDef;
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typedef enum {
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I2S_CPOL_Low = 0x0000, ///< The clock is low in idle state.
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I2S_CPOL_High = SPI_CCR_CPOL ///< The clock is high in idle state.
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} SPI_I2S_CPOL_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief SPI Init structure definition
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////////////////////////////////////////////////////////////////////////////////
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typedef struct {
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SPI_Mode_TypeDef SPI_Mode; ///< Specifies the SPI operating mode
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SPI_DataSize_TypeDef SPI_DataSize; ///< Specifies the SPI available data size
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u8 SPI_DataWidth; ///< SPI data length
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SPI_CPOL_TypeDef SPI_CPOL; ///< Specifies the serial clock steady state
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SPI_CPHA_TypeDef SPI_CPHA; ///< Specifies the clock active edge for the bit capture
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SPI_NSS_TypeDef SPI_NSS; ///< Specifies whether the NSS signal is managed by hardware or by software
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SPI_BaudRatePrescaler_TypeDef SPI_BaudRatePrescaler; ///< Specifies the Baud Rate prescaler value which will be
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///< used to configure the transmit and receive SCK clock
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SPI_FirstBit_TypeDef SPI_FirstBit; ///< Specifies whether data transfers start from MSB or LSB bit
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// u16 SPI_length;
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} SPI_InitTypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief I2S Init structure definition
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////////////////////////////////////////////////////////////////////////////////
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typedef struct {
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SPI_I2S_TRANS_MODE_TypeDef I2S_Mode; ///< Specifies the I2S operating mode.
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SPI_I2S_STANDARD_TypeDef I2S_Standard; ///< Specifies the standard used for the I2S communication.
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SPI_I2S_DATAFORMAT_TypeDef I2S_DataFormat; ///< Specifies the data format for the I2S communication.
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SPI_I2S_MCLK_OUTPUT_TypeDef I2S_MCLKOutput; ///< Specifies whether the I2S MCLK output is enabled or not.
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SPI_I2S_AUDIO_FREQ_TypeDef I2S_AudioFreq; ///< Specifies the frequency selected for the I2S communication.
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SPI_I2S_CPOL_TypeDef I2S_CPOL; ///< Specifies the idle state of the I2S clock.
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} I2S_InitTypeDef;
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup SPI_Exported_Constants
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup SPI_Register_Mask
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/// @{
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#define GCR_Mask ((u32)0x0FFF)
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#define CCR_Mask ((u32)0x003F)
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#define BRR_Mask ((u32)0xFFFF)
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#define ECR_Mask ((u32)0x001F)
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/// @}
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// SPI_7bit_8bit data width
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#define SPI_DataWidth_1b ((u16)0x0001)
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#define SPI_DataWidth_2b ((u16)0x0002)
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#define SPI_DataWidth_3b ((u16)0x0003)
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#define SPI_DataWidth_4b ((u16)0x0004)
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#define SPI_DataWidth_5b ((u16)0x0005)
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#define SPI_DataWidth_6b ((u16)0x0006)
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#define SPI_DataWidth_7b ((u16)0x0007)
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#define SPI_DataWidth_8b ((u16)0x0008)
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#define SPI_DataWidth_9b ((u16)0x0009)
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#define SPI_DataWidth_10b ((u16)0x000a)
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#define SPI_DataWidth_11b ((u16)0x000b)
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#define SPI_DataWidth_12b ((u16)0x000c)
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#define SPI_DataWidth_13b ((u16)0x000d)
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#define SPI_DataWidth_14b ((u16)0x000e)
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#define SPI_DataWidth_15b ((u16)0x000f)
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#define SPI_DataWidth_16b ((u16)0x0010)
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#define SPI_DataWidth_17b ((u16)0x0011)
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#define SPI_DataWidth_18b ((u16)0x0012)
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#define SPI_DataWidth_19b ((u16)0x0013)
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#define SPI_DataWidth_20b ((u16)0x0014)
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#define SPI_DataWidth_21b ((u16)0x0015)
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#define SPI_DataWidth_22b ((u16)0x0016)
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#define SPI_DataWidth_23b ((u16)0x0017)
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#define SPI_DataWidth_24b ((u16)0x0018)
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#define SPI_DataWidth_25b ((u16)0x0019)
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#define SPI_DataWidth_26b ((u16)0x001a)
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#define SPI_DataWidth_27b ((u16)0x001b)
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#define SPI_DataWidth_28b ((u16)0x001c)
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#define SPI_DataWidth_29b ((u16)0x001d)
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#define SPI_DataWidth_30b ((u16)0x001e)
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#define SPI_DataWidth_31b ((u16)0x001f)
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#define SPI_DataWidth_32b ((u16)0x0000)
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup SPI_Exported_Variables
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/// @{
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#ifdef _HAL_SPI_C_
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#define GLOBAL
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#else
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#define GLOBAL extern
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#endif
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#undef GLOBAL
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup SPI_Exported_Functions
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/// @{
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void SPI_DeInit(SPI_TypeDef* spi);
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void SPI_Init(SPI_TypeDef* spi, SPI_InitTypeDef* init_struct);
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void SPI_StructInit(SPI_InitTypeDef* init_struct);
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void SPI_Cmd(SPI_TypeDef* spi, FunctionalState state);
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void SPI_ITConfig(SPI_TypeDef* spi, u8 interrupt, FunctionalState state);
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void SPI_DMACmd(SPI_TypeDef* spi, FunctionalState state);
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void SPI_FifoTrigger(SPI_TypeDef* spi, SPI_TLF_TypeDef fifo_trigger_value, FunctionalState state);
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void SPI_SendData(SPI_TypeDef* spi, u32 data);
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void SPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state);
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void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* spi, SPI_NSS_TypeDef nss);
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void SPI_BiDirectionalLineConfig(SPI_TypeDef* spi, SPI_Direction_TypeDef direction);
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void SPI_ClearITPendingBit(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt);
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void SPI_RxBytes(SPI_TypeDef* spi, u16 number);
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void SPI_SlaveAdjust(SPI_TypeDef* spi, SPI_SlaveAdjust_TypeDef adjust_value);
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bool SPI_DataSizeConfig(SPI_TypeDef* spi, u8 data_size);
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void SPI_DataSizeTypeConfig(SPI_TypeDef* spi, SPI_DataSize_TypeDef SPI_DataSize);
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u32 SPI_ReceiveData(SPI_TypeDef* spi);
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FlagStatus SPI_GetFlagStatus(SPI_TypeDef* spi, SPI_FLAG_TypeDef flag);
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ITStatus SPI_GetITStatus(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt);
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////////////////////////////////////////////////////////////////////////////////
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// Extended function interface
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////////////////////////////////////////////////////////////////////////////////
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void exSPI_ITCmd(SPI_TypeDef* spi, FunctionalState state);
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void exSPI_ITConfig(SPI_TypeDef* spi, SPI_IT_TypeDef interrput, FunctionalState state);
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void exSPI_DMACmd(SPI_TypeDef* spi, FunctionalState state);
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void exSPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state);
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void exSPI_DataEdgeAdjust(SPI_TypeDef* spi, SPI_DataEdgeAdjust_TypeDef adjust_value);
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void I2S_Cmd(SPI_TypeDef* spi, FunctionalState state);
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void I2S_Init(SPI_TypeDef* spi, I2S_InitTypeDef* I2S_InitStruct);
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/// @}
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/// @}
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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#endif //__HAL_SPI_H
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////////////////////////////////////////////////////////////////////////////////
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