2021-08-08 16:31:00 +08:00
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#include "drv_common.h"
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#define DRV_THREAD_PRIORITY 18
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#define DRV_THREAD_STACK_SIZE 512
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#define DRV_THREAD_TIMESLICE 5
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enum {
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MSG_UART0_IRQ,
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MSG_UART1_IRQ,
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MSG_UART2_IRQ,
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};
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static rt_thread_t drv_tid = RT_NULL;
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static rt_mq_t drv_mq = RT_NULL;
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void uart0_irq_process(void);
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void uart1_irq_process(void);
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2022-12-12 02:12:03 +08:00
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rt_section(".irq.uart")
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2021-08-08 16:31:00 +08:00
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void uart0_irq_post(void)
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{
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2021-10-02 08:08:50 +08:00
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rt_uint8_t mq_msg = MSG_UART0_IRQ;
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2021-08-08 16:31:00 +08:00
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rt_mq_send(drv_mq, &mq_msg, 1);
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}
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2022-12-12 02:12:03 +08:00
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rt_section(".irq.uart")
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2021-08-08 16:31:00 +08:00
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void uart1_irq_post(void)
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{
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2021-10-02 08:08:50 +08:00
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rt_uint8_t mq_msg = MSG_UART1_IRQ;
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2021-08-08 16:31:00 +08:00
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rt_mq_send(drv_mq, &mq_msg, 1);
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}
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2022-12-12 02:12:03 +08:00
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rt_section(".irq.uart")
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2021-08-08 16:31:00 +08:00
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void uart2_irq_post(void)
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{
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2021-10-02 08:08:50 +08:00
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rt_uint8_t mq_msg = MSG_UART2_IRQ;
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2021-08-08 16:31:00 +08:00
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rt_mq_send(drv_mq, &mq_msg, 1);
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}
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static void drv_thread_entry(void *parameter)
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{
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2021-10-02 08:08:50 +08:00
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rt_uint8_t mq_msg = 0;
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2021-08-08 16:31:00 +08:00
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while (1) {
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rt_mq_recv(drv_mq, &mq_msg, 1, RT_WAITING_FOREVER);
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switch (mq_msg) {
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#ifdef BSP_USING_UART0
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case MSG_UART0_IRQ:
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uart0_irq_process();
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break;
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#endif
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#ifdef BSP_USING_UART1
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case MSG_UART1_IRQ:
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uart1_irq_process();
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break;
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#endif
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#ifdef BSP_USING_UART2
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case MSG_UART2_IRQ:
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uart2_irq_process();
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break;
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#endif
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default:
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break;
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}
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}
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}
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static int drv_thread_init(void)
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{
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drv_mq = rt_mq_create("drv", 1, 128, RT_IPC_FLAG_FIFO);
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drv_tid = rt_thread_create("drv",
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drv_thread_entry,
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RT_NULL,
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DRV_THREAD_STACK_SIZE,
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DRV_THREAD_PRIORITY,
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DRV_THREAD_TIMESLICE);
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if (drv_tid != RT_NULL)
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rt_thread_startup(drv_tid);
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}
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INIT_PREV_EXPORT(drv_thread_init);
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