2018-11-29 17:00:22 +08:00
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/*
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2021-03-08 22:40:39 +08:00
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* Copyright (c) 2006-2021, RT-Thread Development Team
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2018-11-29 17:00:22 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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2019-01-22 10:00:45 +08:00
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* 2018.10.30 SummerGift first version
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2020-03-23 15:35:27 +08:00
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* 2019.03.05 whj4674672 add stm32h7
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2020-10-14 15:02:23 +08:00
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* 2020-10-14 Dozingfiretruck Porting for stm32wbxx
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2018-11-29 17:00:22 +08:00
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*/
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#ifndef __DRV_USART_H__
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#define __DRV_USART_H__
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#include <rtthread.h>
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#include "rtdevice.h"
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#include <rthw.h>
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#include <drv_common.h>
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2019-01-08 11:58:57 +08:00
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#include "drv_dma.h"
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2018-11-29 17:00:22 +08:00
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int rt_hw_usart_init(void);
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2021-01-29 10:28:18 +08:00
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#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
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2020-10-14 15:02:23 +08:00
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|| defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
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2018-11-29 17:00:22 +08:00
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#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
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2020-06-20 14:04:27 +08:00
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#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
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|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
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2018-11-29 17:00:22 +08:00
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#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef
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2021-01-29 10:28:18 +08:00
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#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) */
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2018-11-29 17:00:22 +08:00
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2021-01-29 10:28:18 +08:00
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#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F2) \
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2019-10-03 22:29:13 +08:00
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|| defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \
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2020-10-14 15:02:23 +08:00
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|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
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2018-12-26 10:43:16 +08:00
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#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG
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2020-06-20 14:04:27 +08:00
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#elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \
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|| defined(SOC_SERIES_STM32MP1)
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2018-12-26 10:43:16 +08:00
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#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_IT
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#endif
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2018-11-29 17:00:22 +08:00
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/* stm32 config class */
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struct stm32_uart_config
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{
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const char *name;
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USART_TypeDef *Instance;
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IRQn_Type irq_type;
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2019-01-08 11:58:57 +08:00
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struct dma_config *dma_rx;
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2019-05-03 20:52:31 +08:00
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struct dma_config *dma_tx;
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2018-11-29 17:00:22 +08:00
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};
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/* stm32 uart dirver class */
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struct stm32_uart
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{
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UART_HandleTypeDef handle;
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2019-01-08 11:58:57 +08:00
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struct stm32_uart_config *config;
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2020-03-23 15:35:27 +08:00
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2018-12-26 10:43:16 +08:00
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#ifdef RT_SERIAL_USING_DMA
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2018-11-29 17:00:22 +08:00
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struct
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{
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DMA_HandleTypeDef handle;
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rt_size_t last_index;
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2019-05-03 20:52:31 +08:00
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} dma_rx;
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struct
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{
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DMA_HandleTypeDef handle;
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} dma_tx;
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2018-11-29 17:00:22 +08:00
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#endif
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2019-05-03 20:52:31 +08:00
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rt_uint16_t uart_dma_flag;
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2018-11-29 17:00:22 +08:00
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struct rt_serial_device serial;
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};
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#endif /* __DRV_USART_H__ */
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