76 lines
2.7 KiB
C
76 lines
2.7 KiB
C
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/*
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* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/******************************************************************************
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* @file ck_dmac.h
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* @brief header file for DMAC Driver
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* @version V1.0
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* @date 02. June 2017
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******************************************************************************/
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#ifndef __CK_DMA_H
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#define __CK_DMA_H
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#include <stdio.h>
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#include "soc.h"
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#define CK_DMA_MAXCHANNEL 2
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#define CK_DMA_INT_EN 1
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#define CK_DMA_CH_EN 1
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#define CK_DMA_TFR 0x0002
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#define CK_DMA_ERR 0x0001
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#define CK_DMA_INTC 0x03
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#define CK_DMA_MASK 0x03
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typedef enum {
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DMA_ADDR_INCREMENT = 0,
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DMA_ADDR_DECREMENT = 1,
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DMA_ADDR_NOCHANGE = 2
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} enum_addr_state_e;
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typedef enum {
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DMA_DATAWIDTH_SIZE8 = 1,
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DMA_DATAWIDTH_SIZE16 = 2,
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DMA_DATAWIDTH_SIZE32 = 4
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} dma_datawidth_e;
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typedef enum {
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DMA_HANDSHAKING_HARDWARE = 0,
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DMA_HANDSHAKING_SOFTWARE = 1,
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} dma_handshaking_select_e;
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typedef enum {
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DMA_PRIORITY0 = 0,
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DMA_PRIORITY1 = 1,
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DMA_PRIOTITY2 = 2,
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DMA_PRIOTITY3 = 3
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} dma_priority_t;
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typedef struct {
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__IOM uint32_t SAR; /* offset: 0x00 (R/W) Channel Source Address Register */
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__IOM uint32_t DAR; /* offset: 0x04 (R/W) Channel Destination Address Register */
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__IOM uint32_t CHCTRLA; /* offset: 0x08 (R/W) Channel Control Register A */
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__IOM uint32_t CHCTRLB; /* offset: 0x0C (R/W) Channel Control Register B */
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__IOM uint8_t CHINTM:2; /* offset: 0x10 (R/W) Channel Interrupt Mask Register */
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uint8_t RESERVED0[3];
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__IM uint8_t CHINTS:2; /* offset: 0x14 (R/ ) Channel Interrupt Status Register */
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uint8_t RESERVED1[3];
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__IOM uint8_t CHINTC:2; /* offset: 0x18 (R/W) Channel Interrupt Clear Register */
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uint8_t RESERVED2[3];
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__IOM uint8_t CHSREQ:1; /* offset: 0x1C (R/W) Channel Software Request Register */
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uint8_t RESERVED3[3];
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__IOM uint8_t CHEN:1; /* offset: 0x20 (R/W) Channel Enable Register */
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uint8_t RESERVED4[3];
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} ck_dma_reg_t;
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#endif /* __CK_DMA_H */
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