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rt-thread/bsp/ls1cdev/libraries/ls1c_spi.c

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增加龙芯1c的硬件SPI相关接口
2017-10-23 17:10:48 +08:00
/*
* File : ls1c_spi.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2017-10-23 <EFBFBD><EFBFBD>Ϊ<EFBFBD><EFBFBD> first version
*/
// Ӳ<><D3B2>spi<70>ӿ<EFBFBD>Դ<EFBFBD>ļ<EFBFBD>
#include <string.h>
#include "ls1c_public.h"
#include "ls1c_regs.h"
#include "ls1c_clock.h"
#include "ls1c_spi.h"
// <20>Ĵ<EFBFBD><C4B4><EFBFBD>ƫ<EFBFBD><C6AB>
#define LS1C_SPI_SPCR_OFFSET (0) // <20><><EFBFBD>ƼĴ<C6BC><C4B4><EFBFBD>
#define LS1C_SPI_SPSR_OFFSET (1) // ״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD>
#define LS1C_SPI_TxFIFO_OFFSET (2) // <20><><EFBFBD>͵<EFBFBD><CDB5><EFBFBD><EFBFBD>ݼĴ<DDBC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݼĴ<DDBC><C4B4><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD><C6AB><EFBFBD><EFBFBD>ͬ
#define LS1C_SPI_RxFIFO_OFFSET (2) // <20><><EFBFBD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD>ݼĴ<DDBC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>뷢<EFBFBD><EBB7A2><EFBFBD><EFBFBD><EFBFBD>ݼĴ<DDBC><C4B4><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD><C6AB><EFBFBD><EFBFBD>ͬ
#define LS1C_SPI_SPER_OFFSET (3) // <20>ⲿ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
#define LS1C_SPI_SFC_PARAM_OFFSET (4) // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƼĴ<C6BC><C4B4><EFBFBD>
#define LS1C_SPI_SFC_SOFTCS_OFFSET (5) // Ƭѡ<C6AC><D1A1><EFBFBD>ƼĴ<C6BC><C4B4><EFBFBD>
#define LS1C_SPI_SFC_TIMING_OFFSET (6) // ʱ<><CAB1><EFBFBD><EFBFBD><EFBFBD>ƼĴ<C6BC><C4B4><EFBFBD>
// <20>Ĵ<EFBFBD><C4B4><EFBFBD>SPCR<43>е<EFBFBD>λ<EFBFBD><CEBB>
#define LS1C_SPI_SPCR_SPIE_BIT (7)
#define LS1C_SPI_SPCR_SPIE_MASK (0x01 << LS1C_SPI_SPCR_SPIE_BIT)
#define LS1C_SPI_SPCR_SPE_BIT (6)
#define LS1C_SPI_SPCR_SPE_MASK (0x01 << LS1C_SPI_SPCR_SPE_BIT)
#define LS1C_SPI_SPCR_CPOL_BIT (3)
#define LS1C_SPI_SPCR_CPOL_MASK (0x01 << LS1C_SPI_SPCR_CPOL_BIT)
#define LS1C_SPI_SPCR_CPHA_BIT (2)
#define LS1C_SPI_SPCR_CPHA_MASK (0x01 << LS1C_SPI_SPCR_CPHA_BIT)
#define LS1C_SPI_SPCR_SPR_BIT (0)
#define LS1C_SPI_SPCR_SPR_MASK (0x03 << LS1C_SPI_SPCR_SPR_BIT)
// <20>Ĵ<EFBFBD><C4B4><EFBFBD>SPSR<53>е<EFBFBD>λ<EFBFBD><CEBB>
#define LS1C_SPI_SPSR_SPIF_BIT (7)
#define LS1C_SPI_SPSR_SPIF_MASK (0x01 << LS1C_SPI_SPSR_SPIF_BIT)
#define LS1C_SPI_SPSR_WCOL_BIT (6)
#define LS1C_SPI_SPSR_WCOL_MASK (0x01 << LS1C_SPI_SPSR_WCOL_BIT)
// <20>Ĵ<EFBFBD><C4B4><EFBFBD>SPER<45>е<EFBFBD>λ<EFBFBD><CEBB>
#define LS1C_SPI_SPER_SPRE_BIT (0)
#define LS1C_SPI_SPER_SPRE_MASK (0x3 << LS1C_SPI_SPER_SPRE_BIT)
// <20>Ĵ<EFBFBD><C4B4><EFBFBD>SFC_SOFTCS<43><53>λ<EFBFBD><CEBB>
#define LS1C_SPI_SFC_SOFTCS_CSN_BIT (4)
#define LS1C_SPI_SFC_SOFTCS_CSN_MASK (0x0f << LS1C_SPI_SFC_SOFTCS_CSN_BIT)
#define LS1C_SPI_SFC_SOFTCS_CSEN_BIT (0)
#define LS1C_SPI_SFC_SOFTCS_CSEN_MASK (0x0f << LS1C_SPI_SFC_SOFTCS_CSEN_BIT)
// <20><><EFBFBD>ͳ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
#define LS1C_SPI_TX_TIMEOUT (20000)
/*
* <EFBFBD><EFBFBD>ȡָ<EFBFBD><EFBFBD>SPIģ<EFBFBD><EFBFBD><EFBFBD>Ļ<EFBFBD><EFBFBD><EFBFBD>ַ
* @SPIx SPIģ<EFBFBD><EFBFBD><EFBFBD>ı<EFBFBD><EFBFBD><EFBFBD>
*/
inline void *spi_get_base(ls1c_spi_t SPIx)
{
void *base = NULL;
switch (SPIx)
{
case LS1C_SPI_0:
base = (void *)LS1C_SPI0_BASE;
break;
case LS1C_SPI_1:
base = (void *)LS1C_SPI1_BASE;
break;
default:
base = NULL;
break;
}
return base;
}
/*
* <EFBFBD><EFBFBD>ӡָ<EFBFBD><EFBFBD>SPIģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>мĴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
* @spi_info_p SPIģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
*/
void spi_print_all_regs_info(ls1c_spi_info_t *spi_info_p)
{
void *spi_base = spi_get_base(spi_info_p->SPIx);
rt_kprintf("[%s] SPI%d's info:\r\n\
SPCR=0x%x, SPSR=0x%x, SPER=0x%x, SFC_PARAM=0x%x, SFC_SOFTCS=0x%x, SFC_TIMING=0x%x\r\n",
__FUNCTION__, spi_info_p->SPIx,
reg_read_8(spi_base + LS1C_SPI_SPCR_OFFSET),
reg_read_8(spi_base + LS1C_SPI_SPSR_OFFSET),
reg_read_8(spi_base + LS1C_SPI_SPER_OFFSET),
reg_read_8(spi_base + LS1C_SPI_SFC_PARAM_OFFSET),
reg_read_8(spi_base + LS1C_SPI_SFC_SOFTCS_OFFSET),
reg_read_8(spi_base + LS1C_SPI_SFC_TIMING_OFFSET));
return ;
}
/*
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>SPIʱ<EFBFBD><EFBFBD>Ƶ<EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶϵ<EFBFBD><EFBFBD>
* @max_speed_hz SPI<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD>ٶ<EFBFBD>
* @ret <EFBFBD><EFBFBD>Ƶϵ<EFBFBD><EFBFBD>
*/
unsigned int spi_get_div(unsigned int max_speed_hz)
{
unsigned long clk = 0;
unsigned int div = 0;
unsigned int div_tmp = 0;
unsigned int bit = 0;
clk = clk_get_apb_rate();
div = DIV_ROUND_UP(clk, max_speed_hz);
if (div < 2)
div = 2;
if (div > 4096)
div = 4096;
bit = ls1c_fls(div) - 1;
switch (1 << bit)
{
case 16:
div_tmp = 2;
if (div > (1 << bit))
{
div_tmp++;
}
break;
case 32:
div_tmp = 3;
if (div > (1 << bit))
{
div_tmp += 2;
}
break;
case 8:
div_tmp = 4;
if (div > (1 << bit))
{
div_tmp -= 2;
}
break;
default:
div_tmp = bit - 1;
if (div > (1 << bit))
{
div_tmp++;
}
break;
}
/*
rt_kprintf("[%s] clk=%ld, max_speed_hz=%d, div_tmp=%d, bit=%d\r\n",
__FUNCTION__, clk, max_speed_hz, div_tmp, bit);
*/
return div_tmp;
}
/*
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>
* @spi_info_p SPIģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
*/
void spi_set_clock(ls1c_spi_info_t *spi_info_p)
{
void *spi_base = spi_get_base(spi_info_p->SPIx);
unsigned int div = 0;
unsigned char val = 0;
// <20><>ȡ<EFBFBD><C8A1>Ƶϵ<C6B5><CFB5>
div = spi_get_div(spi_info_p->max_speed_hz);
// <20><><EFBFBD><EFBFBD>spr
val = reg_read_8(spi_base + LS1C_SPI_SPCR_OFFSET);
val &= (~LS1C_SPI_SPCR_SPR_MASK); // spr<70><72><EFBFBD><EFBFBD>
val |= (div & LS1C_SPI_SPCR_SPR_MASK); // <20><><EFBFBD><EFBFBD><EFBFBD>µ<EFBFBD>spr
reg_write_8(val, spi_base + LS1C_SPI_SPCR_OFFSET);
// <20><><EFBFBD><EFBFBD>spre
val = reg_read_8(spi_base + LS1C_SPI_SPER_OFFSET);
val &= (~LS1C_SPI_SPER_SPRE_MASK); // spre<72><65><EFBFBD><EFBFBD>
val |= ((div >> 2) & LS1C_SPI_SPER_SPRE_MASK); // <20><><EFBFBD><EFBFBD><EFBFBD>µ<EFBFBD>spre
reg_write_8(val, spi_base + LS1C_SPI_SPER_OFFSET);
return ;
}
/*
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD>ģʽ(ʱ<EFBFBD>Ӽ<EFBFBD><EFBFBD>Ժ<EFBFBD><EFBFBD><EFBFBD>λ)
* @spi_info_p SPIģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
*/
void spi_set_mode(ls1c_spi_info_t *spi_info_p)
{
void *spi_base = spi_get_base(spi_info_p->SPIx);
unsigned char val = 0;
val = reg_read_8(spi_base + LS1C_SPI_SPCR_OFFSET);
// <20><><EFBFBD><EFBFBD>ʱ<EFBFBD>Ӽ<EFBFBD><D3BC><EFBFBD>--cpol
val &= (~LS1C_SPI_SPCR_CPOL_MASK); // cpol<6F><6C>0
val |= (spi_info_p->cpol << LS1C_SPI_SPCR_CPOL_BIT); // д<><D0B4><EFBFBD>µ<EFBFBD>cpol
// <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>λ--cpha
val &= (~LS1C_SPI_SPCR_CPHA_MASK); // cpha<68><61>0
val |= (spi_info_p->cpha << LS1C_SPI_SPCR_CPHA_BIT); // д<><D0B4><EFBFBD>µ<EFBFBD>cpha
reg_write_8(val, spi_base + LS1C_SPI_SPCR_OFFSET);
return ;
}
/*
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><EFBFBD>ƬѡΪָ<EFBFBD><EFBFBD>״̬
* @spi_info_p SPIģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
* @new_status Ƭѡ<EFBFBD><EFBFBD><EFBFBD>ŵ<EFBFBD><EFBFBD><EFBFBD>״̬<EFBFBD><EFBFBD>ȡֵΪ0<EFBFBD><EFBFBD>1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߵ<EFBFBD>ƽ<EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD>ƽ
*/
void spi_set_cs(ls1c_spi_info_t *spi_info_p, int new_status)
{
void *spi_base = spi_get_base(spi_info_p->SPIx);
unsigned char cs = spi_info_p->cs;
unsigned char val = 0;
val = 0xf0 | (0x01 << cs); // ȫ<><C8AB>csn=1<><31>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>csen=1
if (new_status) // cs = 1
{
val |= (0x10 << cs); // ָ<><D6B8>csn=1
}
else // cs = 0
{
val &= ~(0x10 << cs); // ָ<><D6B8>csn=0
}
reg_write_8(val, spi_base + LS1C_SPI_SFC_SOFTCS_OFFSET);
return ;
}
/*
* <EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>ָ<EFBFBD><EFBFBD>SPIģ<EFBFBD><EFBFBD>
* @spi_info_p SPIģ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
*/
void spi_init(ls1c_spi_info_t *spi_info_p)
{
void *spi_base = spi_get_base(spi_info_p->SPIx);
unsigned char val = 0;
// ʹ<><CAB9>SPI<50><49><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>masterģʽ<C4A3><CABD><EFBFBD>ر<EFBFBD><D8B1>ж<EFBFBD>
reg_write_8(0x53, spi_base + LS1C_SPI_SPCR_OFFSET);
// <20><><EFBFBD><EFBFBD>״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD>
reg_write_8(0xc0, spi_base + LS1C_SPI_SPSR_OFFSET);
// 1<>ֽڲ<D6BD><DAB2><EFBFBD><EFBFBD>жϣ<D0B6><CFA3><EFBFBD><EFBFBD><EFBFBD>(<28><>)<29>뷢<EFBFBD><EBB7A2>(д)ʱ<><CAB1>ͬʱ
reg_write_8(0x03, spi_base + LS1C_SPI_SPER_OFFSET);
// <20>ر<EFBFBD>SPI flash
val = reg_read_8(spi_base + LS1C_SPI_SFC_PARAM_OFFSET);
val &= 0xfe;
reg_write_8(val, spi_base + LS1C_SPI_SFC_PARAM_OFFSET);
// spi flashʱ<68><CAB1><EFBFBD><EFBFBD><EFBFBD>ƼĴ<C6BC><C4B4><EFBFBD>
reg_write_8(0x05, spi_base + LS1C_SPI_SFC_TIMING_OFFSET);
// <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
spi_set_clock(spi_info_p);
// <20><><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>ģʽ(ʱ<>Ӽ<EFBFBD><D3BC>Ժ<EFBFBD><D4BA><EFBFBD>λ)
spi_set_mode(spi_info_p);
// <20><>ӡ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>Ϣ(<28><><EFBFBD>ڵ<EFBFBD><DAB5><EFBFBD>)
// spi_print_all_regs_info(spi_info_p);
return ;
}
/*
* <EFBFBD>ȴ<EFBFBD><EFBFBD>շ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
inline void spi_wait_txrx_done(ls1c_spi_info_t *spi_info_p)
{
void *spi_base = spi_get_base(spi_info_p->SPIx);
int timeout = LS1C_SPI_TX_TIMEOUT;
while (timeout--)
{
if (LS1C_SPI_SPSR_SPIF_MASK & reg_read_8(spi_base + LS1C_SPI_SPSR_OFFSET))
break;
}
return ;
}
/*
* <EFBFBD><EFBFBD><EFBFBD>жϺͱ<EFBFBD>־λ
*/
inline void spi_clear(ls1c_spi_info_t *spi_info_p)
{
void *spi_base = spi_get_base(spi_info_p->SPIx);
unsigned char val = 0;
// <20><><EFBFBD>ж<EFBFBD>
val = reg_read_8(spi_base + LS1C_SPI_SPSR_OFFSET);
val |= LS1C_SPI_SPSR_SPIF_MASK;
reg_write_8(val, spi_base + LS1C_SPI_SPSR_OFFSET);
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־λ(Write-Collision Clear)
val = reg_read_8(spi_base + LS1C_SPI_SPSR_OFFSET);
if (LS1C_SPI_SPSR_WCOL_MASK & val)
{
rt_kprintf("[%s] clear register SPSR's wcol!\r\n"); // <20>ֲ<EFBFBD><D6B2><EFBFBD>linuxԴ<78><D4B4><EFBFBD>в<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>Ӹ<EFBFBD><D3B8><EFBFBD>ӡ<EFBFBD><D3A1><EFBFBD><EFBFBD>
reg_write_8(val & ~LS1C_SPI_SPSR_WCOL_MASK, spi_base + LS1C_SPI_SPSR_OFFSET); // д0<D0B4><30>linuxԴ<78><D4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д0
// reg_write_8(val | LS1C_SPI_SPSR_WCOL_MASK, spi_base + LS1C_SPI_SPSR_OFFSET); // д1<D0B4><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1c<31>ֲᣬӦ<E1A3AC><D3A6>д1
}
return ;
}
/*
* ͨ<EFBFBD><EFBFBD>ָ<EFBFBD><EFBFBD>SPI<EFBFBD><EFBFBD><EFBFBD>ͽ<EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD>
* ע<EFBFBD>⣬<EFBFBD>ڶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵͳ<EFBFBD>У<EFBFBD><EFBFBD>˺<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD>⡣
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>֤<EFBFBD>ں<EFBFBD>ij<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>շ<EFBFBD>ij<EFBFBD><EFBFBD><EFBFBD>ֽڵĹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܱ<EFBFBD><EFBFBD>л<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͬʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͬһ<EFBFBD><EFBFBD>SPI<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵĴ<EFBFBD><EFBFBD>豸ͨ<EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD>Ϊ<EFBFBD><EFBFBD>о1c<EFBFBD><EFBFBD>ÿ·SPI<EFBFBD>Ͽ<EFBFBD><EFBFBD>ܽ<EFBFBD><EFBFBD>в<EFBFBD>ͬ<EFBFBD>Ĵ<EFBFBD><EFBFBD>豸<EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD>Ƶ<EFBFBD>ʡ<EFBFBD>ģʽ<EFBFBD>ȿ<EFBFBD><EFBFBD>ܲ<EFBFBD>ͬ
* @spi_info_p SPI<EFBFBD>ӿ<EFBFBD>
* @tx_ch <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @ret <EFBFBD>յ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*/
unsigned char spi_txrx_byte(ls1c_spi_info_t *spi_info_p, unsigned char tx_ch)
{
void *spi_base = spi_get_base(spi_info_p->SPIx);
unsigned char rx_ch = 0;
// <20>շ<EFBFBD><D5B7><EFBFBD><EFBFBD><EFBFBD>
reg_write_8(tx_ch, spi_base + LS1C_SPI_TxFIFO_OFFSET); // <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
spi_wait_txrx_done(spi_info_p); // <20>ȴ<EFBFBD><C8B4>շ<EFBFBD><D5B7><EFBFBD><EFBFBD><EFBFBD>
rx_ch = reg_read_8(spi_base + LS1C_SPI_RxFIFO_OFFSET); // <20><>ȡ<EFBFBD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
spi_clear(spi_info_p); // <20><><EFBFBD>жϺͱ<CFBA>־λ
return rx_ch;
}