370 lines
13 KiB
C
370 lines
13 KiB
C
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/*
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* Copyright (c) 2014, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*
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* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
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*
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* This file was generated automatically and any changes may be lost.
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*/
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#ifndef __HW_VREF_REGISTERS_H__
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#define __HW_VREF_REGISTERS_H__
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#include "regs.h"
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/*
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* MK64F12 VREF
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*
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* Voltage Reference
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*
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* Registers defined in this header file:
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* - HW_VREF_TRM - VREF Trim Register
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* - HW_VREF_SC - VREF Status and Control Register
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*
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* - hw_vref_t - Struct containing all module registers.
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*/
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//! @name Module base addresses
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//@{
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#ifndef REGS_VREF_BASE
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#define HW_VREF_INSTANCE_COUNT (1U) //!< Number of instances of the VREF module.
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#define REGS_VREF_BASE (0x40074000U) //!< Base address for VREF.
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_VREF_TRM - VREF Trim Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_VREF_TRM - VREF Trim Register (RW)
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*
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* Reset value: 0x00U
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*
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* This register contains bits that contain the trim data for the Voltage
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* Reference.
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*/
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typedef union _hw_vref_trm
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{
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uint8_t U;
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struct _hw_vref_trm_bitfields
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{
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uint8_t TRIM : 6; //!< [5:0] Trim bits
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uint8_t CHOPEN : 1; //!< [6] Chop oscillator enable. When set,
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//! internal chopping operation is enabled and the internal analog offset will
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//! be minimized.
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uint8_t RESERVED0 : 1; //!< [7]
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} B;
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} hw_vref_trm_t;
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#endif
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/*!
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* @name Constants and macros for entire VREF_TRM register
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*/
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//@{
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#define HW_VREF_TRM_ADDR (REGS_VREF_BASE + 0x0U)
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#ifndef __LANGUAGE_ASM__
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#define HW_VREF_TRM (*(__IO hw_vref_trm_t *) HW_VREF_TRM_ADDR)
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#define HW_VREF_TRM_RD() (HW_VREF_TRM.U)
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#define HW_VREF_TRM_WR(v) (HW_VREF_TRM.U = (v))
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#define HW_VREF_TRM_SET(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() | (v)))
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#define HW_VREF_TRM_CLR(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() & ~(v)))
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#define HW_VREF_TRM_TOG(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() ^ (v)))
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#endif
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//@}
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/*
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* Constants & macros for individual VREF_TRM bitfields
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*/
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/*!
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* @name Register VREF_TRM, field TRIM[5:0] (RW)
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*
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* These bits change the resulting VREF by approximately +/- 0.5 mV for each
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* step. Min = minimum and max = maximum voltage reference output. For minimum and
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* maximum voltage reference output values, refer to the Data Sheet for this chip.
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*
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* Values:
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* - 000000 - Min
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* - 111111 - Max
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*/
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//@{
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#define BP_VREF_TRM_TRIM (0U) //!< Bit position for VREF_TRM_TRIM.
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#define BM_VREF_TRM_TRIM (0x3FU) //!< Bit mask for VREF_TRM_TRIM.
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#define BS_VREF_TRM_TRIM (6U) //!< Bit field size in bits for VREF_TRM_TRIM.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the VREF_TRM_TRIM field.
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#define BR_VREF_TRM_TRIM (HW_VREF_TRM.B.TRIM)
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#endif
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//! @brief Format value for bitfield VREF_TRM_TRIM.
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#define BF_VREF_TRM_TRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_TRM_TRIM), uint8_t) & BM_VREF_TRM_TRIM)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the TRIM field to a new value.
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#define BW_VREF_TRM_TRIM(v) (HW_VREF_TRM_WR((HW_VREF_TRM_RD() & ~BM_VREF_TRM_TRIM) | BF_VREF_TRM_TRIM(v)))
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#endif
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//@}
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/*!
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* @name Register VREF_TRM, field CHOPEN[6] (RW)
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*
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* This bit is set during factory trimming of the VREF voltage. This bit should
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* be written to 1 to achieve the performance stated in the data sheet.
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*
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* Values:
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* - 0 - Chop oscillator is disabled.
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* - 1 - Chop oscillator is enabled.
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*/
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//@{
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#define BP_VREF_TRM_CHOPEN (6U) //!< Bit position for VREF_TRM_CHOPEN.
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#define BM_VREF_TRM_CHOPEN (0x40U) //!< Bit mask for VREF_TRM_CHOPEN.
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#define BS_VREF_TRM_CHOPEN (1U) //!< Bit field size in bits for VREF_TRM_CHOPEN.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the VREF_TRM_CHOPEN field.
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#define BR_VREF_TRM_CHOPEN (BITBAND_ACCESS8(HW_VREF_TRM_ADDR, BP_VREF_TRM_CHOPEN))
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#endif
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//! @brief Format value for bitfield VREF_TRM_CHOPEN.
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#define BF_VREF_TRM_CHOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_TRM_CHOPEN), uint8_t) & BM_VREF_TRM_CHOPEN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the CHOPEN field to a new value.
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#define BW_VREF_TRM_CHOPEN(v) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR, BP_VREF_TRM_CHOPEN) = (v))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_VREF_SC - VREF Status and Control Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_VREF_SC - VREF Status and Control Register (RW)
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*
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* Reset value: 0x00U
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*
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* This register contains the control bits used to enable the internal voltage
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* reference and to select the buffer mode to be used.
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*/
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typedef union _hw_vref_sc
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{
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uint8_t U;
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struct _hw_vref_sc_bitfields
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{
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uint8_t MODE_LV : 2; //!< [1:0] Buffer Mode selection
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uint8_t VREFST : 1; //!< [2] Internal Voltage Reference stable
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uint8_t RESERVED0 : 2; //!< [4:3]
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uint8_t ICOMPEN : 1; //!< [5] Second order curvature compensation
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//! enable
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uint8_t REGEN : 1; //!< [6] Regulator enable
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uint8_t VREFEN : 1; //!< [7] Internal Voltage Reference enable
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} B;
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} hw_vref_sc_t;
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#endif
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/*!
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* @name Constants and macros for entire VREF_SC register
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*/
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//@{
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#define HW_VREF_SC_ADDR (REGS_VREF_BASE + 0x1U)
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#ifndef __LANGUAGE_ASM__
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#define HW_VREF_SC (*(__IO hw_vref_sc_t *) HW_VREF_SC_ADDR)
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#define HW_VREF_SC_RD() (HW_VREF_SC.U)
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#define HW_VREF_SC_WR(v) (HW_VREF_SC.U = (v))
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#define HW_VREF_SC_SET(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() | (v)))
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#define HW_VREF_SC_CLR(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() & ~(v)))
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#define HW_VREF_SC_TOG(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() ^ (v)))
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#endif
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//@}
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/*
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* Constants & macros for individual VREF_SC bitfields
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*/
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/*!
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* @name Register VREF_SC, field MODE_LV[1:0] (RW)
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*
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* These bits select the buffer modes for the Voltage Reference module.
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*
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* Values:
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* - 00 - Bandgap on only, for stabilization and startup
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* - 01 - High power buffer mode enabled
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* - 10 - Low-power buffer mode enabled
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* - 11 - Reserved
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*/
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//@{
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#define BP_VREF_SC_MODE_LV (0U) //!< Bit position for VREF_SC_MODE_LV.
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#define BM_VREF_SC_MODE_LV (0x03U) //!< Bit mask for VREF_SC_MODE_LV.
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#define BS_VREF_SC_MODE_LV (2U) //!< Bit field size in bits for VREF_SC_MODE_LV.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the VREF_SC_MODE_LV field.
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#define BR_VREF_SC_MODE_LV (HW_VREF_SC.B.MODE_LV)
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#endif
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//! @brief Format value for bitfield VREF_SC_MODE_LV.
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#define BF_VREF_SC_MODE_LV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_MODE_LV), uint8_t) & BM_VREF_SC_MODE_LV)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the MODE_LV field to a new value.
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#define BW_VREF_SC_MODE_LV(v) (HW_VREF_SC_WR((HW_VREF_SC_RD() & ~BM_VREF_SC_MODE_LV) | BF_VREF_SC_MODE_LV(v)))
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#endif
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//@}
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/*!
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* @name Register VREF_SC, field VREFST[2] (RO)
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*
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* This bit indicates that the bandgap reference within the Voltage Reference
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* module has completed its startup and stabilization.
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*
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* Values:
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* - 0 - The module is disabled or not stable.
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* - 1 - The module is stable.
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*/
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//@{
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#define BP_VREF_SC_VREFST (2U) //!< Bit position for VREF_SC_VREFST.
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#define BM_VREF_SC_VREFST (0x04U) //!< Bit mask for VREF_SC_VREFST.
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#define BS_VREF_SC_VREFST (1U) //!< Bit field size in bits for VREF_SC_VREFST.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the VREF_SC_VREFST field.
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#define BR_VREF_SC_VREFST (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFST))
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#endif
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//@}
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/*!
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* @name Register VREF_SC, field ICOMPEN[5] (RW)
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*
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* This bit is set during factory trimming of the VREF voltage. This bit should
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* be written to 1 to achieve the performance stated in the data sheet.
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*
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* Values:
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* - 0 - Disabled
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* - 1 - Enabled
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*/
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//@{
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#define BP_VREF_SC_ICOMPEN (5U) //!< Bit position for VREF_SC_ICOMPEN.
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#define BM_VREF_SC_ICOMPEN (0x20U) //!< Bit mask for VREF_SC_ICOMPEN.
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#define BS_VREF_SC_ICOMPEN (1U) //!< Bit field size in bits for VREF_SC_ICOMPEN.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the VREF_SC_ICOMPEN field.
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#define BR_VREF_SC_ICOMPEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_ICOMPEN))
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#endif
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//! @brief Format value for bitfield VREF_SC_ICOMPEN.
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#define BF_VREF_SC_ICOMPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_ICOMPEN), uint8_t) & BM_VREF_SC_ICOMPEN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the ICOMPEN field to a new value.
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#define BW_VREF_SC_ICOMPEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_ICOMPEN) = (v))
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#endif
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//@}
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/*!
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* @name Register VREF_SC, field REGEN[6] (RW)
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*
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* This bit is used to enable the internal 1.75 V regulator to produce a
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* constant internal voltage supply in order to reduce the sensitivity to external
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* supply noise and variation. If it is desired to keep the regulator enabled in very
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* low power modes, refer to the Chip Configuration details for a description on
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* how this can be achieved. This bit is set during factory trimming of the VREF
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* voltage. This bit should be written to 1 to achieve the performance stated in
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* the data sheet.
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*
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* Values:
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* - 0 - Internal 1.75 V regulator is disabled.
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* - 1 - Internal 1.75 V regulator is enabled.
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*/
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//@{
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#define BP_VREF_SC_REGEN (6U) //!< Bit position for VREF_SC_REGEN.
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#define BM_VREF_SC_REGEN (0x40U) //!< Bit mask for VREF_SC_REGEN.
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#define BS_VREF_SC_REGEN (1U) //!< Bit field size in bits for VREF_SC_REGEN.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the VREF_SC_REGEN field.
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#define BR_VREF_SC_REGEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_REGEN))
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#endif
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//! @brief Format value for bitfield VREF_SC_REGEN.
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#define BF_VREF_SC_REGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_REGEN), uint8_t) & BM_VREF_SC_REGEN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the REGEN field to a new value.
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#define BW_VREF_SC_REGEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_REGEN) = (v))
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#endif
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//@}
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/*!
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* @name Register VREF_SC, field VREFEN[7] (RW)
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*
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* This bit is used to enable the bandgap reference within the Voltage Reference
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* module. After the VREF is enabled, turning off the clock to the VREF module
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* via the corresponding clock gate register will not disable the VREF. VREF must
|
||
|
|
* be disabled via this VREFEN bit.
|
||
|
|
*
|
||
|
|
* Values:
|
||
|
|
* - 0 - The module is disabled.
|
||
|
|
* - 1 - The module is enabled.
|
||
|
|
*/
|
||
|
|
//@{
|
||
|
|
#define BP_VREF_SC_VREFEN (7U) //!< Bit position for VREF_SC_VREFEN.
|
||
|
|
#define BM_VREF_SC_VREFEN (0x80U) //!< Bit mask for VREF_SC_VREFEN.
|
||
|
|
#define BS_VREF_SC_VREFEN (1U) //!< Bit field size in bits for VREF_SC_VREFEN.
|
||
|
|
|
||
|
|
#ifndef __LANGUAGE_ASM__
|
||
|
|
//! @brief Read current value of the VREF_SC_VREFEN field.
|
||
|
|
#define BR_VREF_SC_VREFEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFEN))
|
||
|
|
#endif
|
||
|
|
|
||
|
|
//! @brief Format value for bitfield VREF_SC_VREFEN.
|
||
|
|
#define BF_VREF_SC_VREFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_VREFEN), uint8_t) & BM_VREF_SC_VREFEN)
|
||
|
|
|
||
|
|
#ifndef __LANGUAGE_ASM__
|
||
|
|
//! @brief Set the VREFEN field to a new value.
|
||
|
|
#define BW_VREF_SC_VREFEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFEN) = (v))
|
||
|
|
#endif
|
||
|
|
//@}
|
||
|
|
|
||
|
|
//-------------------------------------------------------------------------------------------
|
||
|
|
// hw_vref_t - module struct
|
||
|
|
//-------------------------------------------------------------------------------------------
|
||
|
|
/*!
|
||
|
|
* @brief All VREF module registers.
|
||
|
|
*/
|
||
|
|
#ifndef __LANGUAGE_ASM__
|
||
|
|
#pragma pack(1)
|
||
|
|
typedef struct _hw_vref
|
||
|
|
{
|
||
|
|
__IO hw_vref_trm_t TRM; //!< [0x0] VREF Trim Register
|
||
|
|
__IO hw_vref_sc_t SC; //!< [0x1] VREF Status and Control Register
|
||
|
|
} hw_vref_t;
|
||
|
|
#pragma pack()
|
||
|
|
|
||
|
|
//! @brief Macro to access all VREF registers.
|
||
|
|
//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
|
||
|
|
//! use the '&' operator, like <code>&HW_VREF</code>.
|
||
|
|
#define HW_VREF (*(hw_vref_t *) REGS_VREF_BASE)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif // __HW_VREF_REGISTERS_H__
|
||
|
|
// v22/130726/0.9
|
||
|
|
// EOF
|