414 lines
13 KiB
C
414 lines
13 KiB
C
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/**
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*******************************************************************************
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* @file hc32f4a0_hrpwm.c
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* @brief This file provides firmware functions to manage the High Resolution
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* Pulse-Width Modulation(HRPWM).
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@verbatim
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Change Logs:
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Date Author Notes
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2020-06-12 Wangmin First version
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2020-09-07 Wangmin Modify channel delay configure function
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parameter type.
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2020-10-13 Wangmin Define variable for count as __IO type
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32f4a0_hrpwm.h"
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#include "hc32f4a0_utility.h"
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/**
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* @addtogroup HC32F4A0_DDL_Driver
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* @{
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*/
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/**
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* @defgroup DDL_HRPWM HRPWM
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* @brief HRPWM Driver Library
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* @{
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*/
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#if (DDL_HRPWM_ENABLE == DDL_ON)
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/*******************************************************************************
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* Local type definitions ('typedef')
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******************************************************************************/
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/*******************************************************************************
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* Local pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup HRPWM_Local_Macros HRPWM Local Macros
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* @{
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*/
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/* About 1mS timeout */
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#define HRPWM_CAL_TIMEOUT (HCLK_VALUE/1000UL)
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#define HRPWM_PCLK0_MIN (120000000UL)
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#define HRPWM_SYSCLKSOURCE_HRC (0x00U)
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#define HRPWM_SYSCLKSOURCE_MRC (0x01U)
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#define HRPWM_SYSCLKSOURCE_LRC (0x02U)
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#define HRPWM_SYSCLKSOURCE_XTAL (0x03U)
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#define HRPWM_SYSCLKSOURCE_XTAL32 (0x04U)
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#define HRPWM_SYSCLKSOURCE_PLLH (0x05U)
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#define HRPWM_PLLSRC_XTAL (0x00UL)
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#define HRPWM_PLLSRC_HRC (0x01UL)
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/**
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* @defgroup HRPWM_Check_Parameters_Validity HRPWM Check Parameters Validity
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* @{
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*/
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/*! Parameter valid check for HRPWM output channel */
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#define IS_VALID_HRPWM_CH(x) \
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( ((x) >= HRPWM_CH_MIN) && \
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((x) <= HRPWM_CH_MAX))
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/*! Parameter valid check for HRPWM caliration unit */
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#define IS_VALID_HRPWM_CAL_UNIT(x) \
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( (HRPWM_CAL_UNIT0 == (x)) || \
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(HRPWM_CAL_UNIT1 == (x)))
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*******************************************************************************
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* Global variable definitions (declared in header file with 'extern')
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******************************************************************************/
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/*******************************************************************************
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* Local function prototypes ('static')
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******************************************************************************/
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/*******************************************************************************
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* Local variable definitions ('static')
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******************************************************************************/
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/*******************************************************************************
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* Function implementation - global ('extern') and local ('static')
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******************************************************************************/
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/**
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* @defgroup HRPWM_Global_Functions HRPWM Global Functions
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* @{
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*/
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/**
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* @brief Process for getting HRPWM Calibrate function code
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* @param [in] u32Unit Calibrate unit, the parameter should be HRPWM_CAL_UNIT0 or HRPWM_CAL_UNIT1
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* @param [out] pu8Code The pointer to get calibrate code.
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* @retval Ok: Success
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* @retval ErrorTimeout: Time out
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* @retval ErrorInvalidParameter: Parameter error
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*/
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en_result_t HRPWM_CalibrateProcess(uint32_t u32Unit, uint8_t* pu8Code)
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{
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__IO uint32_t u32Timeout = HRPWM_CAL_TIMEOUT;
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en_result_t enRet = Ok;
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if(NULL != pu8Code)
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{
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/* Enable calibrate */
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HRPWM_CalibrateCmd(u32Unit, Enable);
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/* Wait calibrate finish flag */
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while(Disable == HRPWM_GetCalibrateStd(u32Unit))
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{
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if(0UL == u32Timeout--)
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{
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enRet = ErrorTimeout;
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break;
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}
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}
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if(Ok == enRet)
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{
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/* Get calibrate code */
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*pu8Code = HRPWM_GetCalCode(u32Unit);
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}
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}
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else
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{
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enRet = ErrorInvalidParameter;
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}
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return enRet;
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}
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/**
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* @brief HRPWM Calibrate function enable or disable for specified unit
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* @param [in] u32Unit Calibrate unit, the parameter should be HRPWM_CAL_UNIT0 or HRPWM_CAL_UNIT1
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* @param [in] enNewState Disable or Enable the function
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* @retval None
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*/
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void HRPWM_CalibrateCmd(uint32_t u32Unit, en_functional_state_t enNewState)
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{
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__IO uint32_t *CALCRx;
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/* Check parameters */
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DDL_ASSERT(IS_VALID_HRPWM_CAL_UNIT(u32Unit));
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DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
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CALCRx = (__IO uint32_t*)(((uint32_t)&M4_HRPWM->CALCR0) + 4UL*u32Unit);
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if(Enable == enNewState)
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{
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SET_REG32_BIT(*CALCRx, HRPWM_CALCR_CALEN);
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}
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else
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{
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CLEAR_REG32_BIT(*CALCRx, HRPWM_CALCR_CALEN);
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}
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}
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/**
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* @brief HRPWM Calibrate function status get for specified unit
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* @param [in] u32Unit Calibrate unit, the parameter should be HRPWM_CAL_UNIT0 or HRPWM_CAL_UNIT1
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* @retval Enable: Calibration function is on.
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* @retval Disable: Calibration function is off.
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*/
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en_functional_state_t HRPWM_GetCalibrateStd(uint32_t u32Unit)
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{
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en_functional_state_t enRet;
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__IO uint32_t *CALCRx;
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/* Check parameters */
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DDL_ASSERT(IS_VALID_HRPWM_CAL_UNIT(u32Unit));
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CALCRx = (__IO uint32_t*)(((uint32_t)&M4_HRPWM->CALCR0) + 4UL*u32Unit);
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if( 0UL != READ_REG32_BIT(*CALCRx, HRPWM_CALCR_ENDF))
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{
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enRet = Enable;
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}
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else
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{
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enRet = Disable;
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}
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return enRet;
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}
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/**
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* @brief HRPWM Calibrate code get for specified unit
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* @param [in] u32Unit Calibrate unit, the parameter should be HRPWM_CAL_UNIT0 or HRPWM_CAL_UNIT1
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* @retval uint8_t: The calibration code.
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*/
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uint8_t HRPWM_GetCalCode(uint32_t u32Unit)
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{
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__IO uint32_t *CALCRx;
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/* Check parameters */
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DDL_ASSERT(IS_VALID_HRPWM_CAL_UNIT(u32Unit));
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CALCRx = (__IO uint32_t*)(((uint32_t)&M4_HRPWM->CALCR0) + 4UL*u32Unit);
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return ((uint8_t)(READ_REG32(*CALCRx)));
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}
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/**
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* @brief HRPWM function enable or disable for specified channel
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* @param [in] u32Ch Channel, the parameter should range from HRPWM_CH_MIN to HRPWM_CH_MAX
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* @param [in] enNewState Disable or Enable the function
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* @retval None
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*/
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void HRPWM_CHCmd(uint32_t u32Ch, en_functional_state_t enNewState)
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{
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__IO uint32_t *CRx;
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/* Check parameters */
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DDL_ASSERT(IS_VALID_HRPWM_CH(u32Ch));
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DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
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CRx = (__IO uint32_t*)(((uint32_t)&M4_HRPWM->CR1) + 4UL*(u32Ch - 1UL));
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if(Enable == enNewState)
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{
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SET_REG32_BIT(*CRx, HRPWM_CR_EN);
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}
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else
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{
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CLEAR_REG32_BIT(*CRx, HRPWM_CR_EN);
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}
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}
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/**
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* @brief HRPWM positive edge adjust enable or disable for specified channel
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* @param [in] u32Ch Channel, the parameter should range from HRPWM_CH_MIN to HRPWM_CH_MAX
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* @param [in] enNewState Disable or Enable the function
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* @retval None
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*/
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void HRPWM_CHPositAdjCmd(uint32_t u32Ch, en_functional_state_t enNewState)
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{
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__IO uint32_t *CRx;
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/* Check parameters */
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DDL_ASSERT(IS_VALID_HRPWM_CH(u32Ch));
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DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
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CRx = (__IO uint32_t*)(((uint32_t)&M4_HRPWM->CR1) + 4UL*(u32Ch - 1UL));
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if(Enable == enNewState)
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{
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SET_REG32_BIT(*CRx, HRPWM_CR_PE);
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}
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else
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{
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CLEAR_REG32_BIT(*CRx, HRPWM_CR_PE);
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}
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}
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/**
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* @brief HRPWM negative edge adjust enable or disable for specified channel
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* @param [in] u32Ch Channel, the parameter should range from HRPWM_CH_MIN to HRPWM_CH_MAX
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* @param [in] enNewState Disable or Enable the function
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* @retval None
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*/
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void HRPWM_CHNegatAdjCmd(uint32_t u32Ch, en_functional_state_t enNewState)
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{
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__IO uint32_t *CRx;
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/* Check parameters */
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DDL_ASSERT(IS_VALID_HRPWM_CH(u32Ch));
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DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
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CRx = (__IO uint32_t*)(((uint32_t)&M4_HRPWM->CR1) + 4UL*(u32Ch - 1UL));
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if(Enable == enNewState)
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{
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SET_REG32_BIT(*CRx, HRPWM_CR_NE);
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}
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else
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{
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CLEAR_REG32_BIT(*CRx, HRPWM_CR_NE);
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}
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}
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/**
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* @brief HRPWM positive edge adjust delay counts configration for specified channel
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* @param [in] u32Ch Channel, the parameter should range from HRPWM_CH_MIN to HRPWM_CH_MAX
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* @param [in] u8DelayNum Delay counts of minimum delay time.
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* @retval None
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*/
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void HRPWM_CHPositCfg(uint32_t u32Ch, uint8_t u8DelayNum)
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{
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__IO uint32_t *CRx;
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/* Check parameters */
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DDL_ASSERT(IS_VALID_HRPWM_CH(u32Ch));
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CRx = (__IO uint32_t*)(((uint32_t)&M4_HRPWM->CR1) + 4UL*(u32Ch - 1UL));
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MODIFY_REG32(*CRx, HRPWM_CR_PSEL, ((uint32_t)u8DelayNum-1UL) << HRPWM_CR_PSEL_POS);
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}
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/**
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* @brief HRPWM negative edge adjust delay counts configration for specified channel
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* @param [in] u32Ch Channel, the parameter should range from HRPWM_CH_MIN to HRPWM_CH_MAX
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* @param [in] u8DelayNum Delay counts of minimum delay time.
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* @retval None
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*/
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void HRPWM_CHNegatCfg(uint32_t u32Ch, uint8_t u8DelayNum)
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{
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__IO uint32_t *CRx;
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/* Check parameters */
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DDL_ASSERT(IS_VALID_HRPWM_CH(u32Ch));
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CRx = (__IO uint32_t*)(((uint32_t)&M4_HRPWM->CR1) + 4UL*(u32Ch - 1UL));
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MODIFY_REG32(*CRx, HRPWM_CR_NSEL, ((uint32_t)u8DelayNum-1UL) << HRPWM_CR_NSEL_POS);
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}
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/**
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* @brief HRPWM Judge the condition of calibration function.
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* @param None
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* @retval Enable: Condition is ready.
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* @retval Disable: Condition is not ready.
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*/
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en_functional_state_t HRPWM_ConditionConfirm(void)
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{
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en_functional_state_t enRet = Enable;
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uint32_t plln;
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uint32_t pllp;
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uint32_t pllm;
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uint32_t sysclkFreq;
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uint32_t pclk0Freq;
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switch (READ_REG8_BIT(M4_CMU->CKSWR, CMU_CKSWR_CKSW))
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{
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case HRPWM_SYSCLKSOURCE_HRC:
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/* HRC is used to system clock */
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sysclkFreq = HRC_VALUE;
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break;
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case HRPWM_SYSCLKSOURCE_MRC:
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/* MRC is used to system clock */
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sysclkFreq = MRC_VALUE;
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break;
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case HRPWM_SYSCLKSOURCE_LRC:
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/* LRC is used to system clock */
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sysclkFreq = LRC_VALUE;
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break;
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case HRPWM_SYSCLKSOURCE_XTAL:
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/* XTAL is used to system clock */
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sysclkFreq = XTAL_VALUE;
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break;
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case HRPWM_SYSCLKSOURCE_XTAL32:
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/* XTAL32 is used to system clock */
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sysclkFreq = HRC_VALUE;
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break;
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case HRPWM_SYSCLKSOURCE_PLLH:
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/* PLLHP is used as system clock. */
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|
pllp = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHP_POS) & 0x0FUL);
|
||
|
|
plln = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHN_POS) & 0xFFUL);
|
||
|
|
pllm = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHM_POS) & 0x03UL);
|
||
|
|
|
||
|
|
/* fpll = ((pllin / pllm) * plln) / pllp */
|
||
|
|
if (HRPWM_PLLSRC_XTAL == READ_REG32_BIT(M4_CMU->PLLHCFGR, CMU_PLLHCFGR_PLLSRC))
|
||
|
|
{
|
||
|
|
sysclkFreq = ((XTAL_VALUE/(pllm + 1UL))*(plln + 1UL))/(pllp + 1UL);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
sysclkFreq = ((HRC_VALUE/(pllm + 1UL))*(plln + 1UL))/(pllp + 1UL);
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
sysclkFreq = HRC_VALUE;
|
||
|
|
enRet = Disable;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if(Enable == enRet)
|
||
|
|
{
|
||
|
|
/* Get pclk0. */
|
||
|
|
pclk0Freq = sysclkFreq >> (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK0S) >> CMU_SCFGR_PCLK0S_POS);
|
||
|
|
|
||
|
|
if(pclk0Freq < HRPWM_PCLK0_MIN)
|
||
|
|
{
|
||
|
|
enRet = Disable;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return enRet;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#endif /* DDL_HRPWM_ENABLE */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/******************************************************************************
|
||
|
|
* EOF (not truncated)
|
||
|
|
*****************************************************************************/
|