204 lines
4.5 KiB
C
204 lines
4.5 KiB
C
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/*!
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\file gd32f30x_rtc.c
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\brief RTC driver
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*/
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/*
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Copyright (C) 2017 GigaDevice
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2017-02-10, V1.0.1, firmware for GD32F30x
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*/
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#include "gd32f30x_rtc.h"
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/*!
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\brief enable RTC interrupt
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\param[in] interrupt: specify which interrupt to enbale
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\arg RTC_INT_SECOND: second interrupt
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\arg RTC_INT_ALARM: alarm interrupt
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\arg RTC_INT_OVERFLOW: overflow interrupt
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\param[out] none
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\retval none
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*/
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void rtc_interrupt_enable(uint32_t interrupt)
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{
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RTC_INTEN |= interrupt;
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}
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/*!
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\brief disable RTC interrupt
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\param[in] interrupt: specify which interrupt to disbale
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\arg RTC_INT_SECOND: second interrupt
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\arg RTC_INT_ALARM: alarm interrupt
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\arg RTC_INT_OVERFLOW: overflow interrupt
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\param[out] none
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\retval none
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*/
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void rtc_interrupt_disable(uint32_t interrupt)
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{
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RTC_INTEN &= ~interrupt;
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}
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/*!
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\brief enter RTC configuration mode
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\param[in] none
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\param[out] none
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\retval none
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*/
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void rtc_configuration_mode_enter(void)
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{
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RTC_CTL |= RTC_CTL_CMF;
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}
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/*!
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\brief exit RTC configuration mode
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\param[in] none
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\param[out] none
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\retval none
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*/
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void rtc_configuration_mode_exit(void)
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{
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RTC_CTL &= ~RTC_CTL_CMF;
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}
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/*!
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\brief wait RTC last write operation finished flag set
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\param[in] none
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\param[out] none
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\retval none
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*/
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void rtc_lwoff_wait(void)
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{
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/* loop until LWOFF flag is set */
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while (RESET == (RTC_CTL & RTC_CTL_LWOFF)){
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}
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}
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/*!
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\brief wait RTC registers synchronized flag set
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\param[in] none
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\param[out] none
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\retval none
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*/
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void rtc_register_sync_wait(void)
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{
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/* clear RSYNF flag */
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RTC_CTL &= ~RTC_CTL_RSYNF;
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/* loop until RSYNF flag is set */
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while (RESET == (RTC_CTL & RTC_CTL_RSYNF)){
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}
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}
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/*!
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\brief get RTC counter value
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\param[in] none
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\param[out] none
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\retval RTC counter value
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*/
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uint32_t rtc_counter_get(void)
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{
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uint32_t temp = 0x0U;
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temp = RTC_CNTL;
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temp |= (RTC_CNTH << 16);
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return temp;
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}
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/*!
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\brief set RTC counter value
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\param[in] cnt: RTC counter value
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\param[out] none
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\retval none
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*/
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void rtc_counter_set(uint32_t cnt)
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{
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rtc_configuration_mode_enter();
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/* set the RTC counter high bits */
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RTC_CNTH = cnt >> 16;
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/* set the RTC counter low bits */
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RTC_CNTL = (cnt & RTC_LOW_VALUE);
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rtc_configuration_mode_exit();
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}
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/*!
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\brief set RTC prescaler value
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\param[in] psc: RTC prescaler value
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\param[out] none
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\retval none
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*/
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void rtc_prescaler_set(uint32_t psc)
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{
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rtc_configuration_mode_enter();
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/* set the RTC prescaler high bits */
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RTC_PSCH = (psc & RTC_HIGH_VALUE) >> 16;
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/* set the RTC prescaler low bits */
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RTC_PSCL = (psc & RTC_LOW_VALUE);
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rtc_configuration_mode_exit();
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}
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/*!
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\brief set RTC alarm value
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\param[in] alarm: RTC alarm value
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\param[out] none
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\retval none
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*/
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void rtc_alarm_config(uint32_t alarm)
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{
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rtc_configuration_mode_enter();
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/* set the alarm high bits */
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RTC_ALRMH = alarm >> 16;
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/* set the alarm low bits */
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RTC_ALRML = (alarm & RTC_LOW_VALUE);
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rtc_configuration_mode_exit();
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}
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/*!
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\brief get RTC divider value
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\param[in] none
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\param[out] none
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\retval RTC divider value
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*/
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uint32_t rtc_divider_get(void)
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{
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uint32_t temp = 0x00U;
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temp = (RTC_DIVH & RTC_DIVH_DIV) << 16;
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temp |= RTC_DIVL;
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return temp;
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}
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/*!
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\brief get RTC flag status
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\param[in] flag: specify which flag status to get
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\arg RTC_FLAG_SECOND: second interrupt flag
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\arg RTC_FLAG_ALARM: alarm interrupt flag
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\arg RTC_FLAG_OVERFLOW: overflow interrupt flag
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\arg RTC_FLAG_RSYN: registers synchronized flag
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\arg RTC_FLAG_LWOF: last write operation finished flag
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\param[out] none
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\retval SET or RESET
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*/
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FlagStatus rtc_flag_get(uint32_t flag)
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{
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if(RESET != (RTC_CTL & flag)){
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return SET;
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}else{
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return RESET;
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}
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}
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/*!
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\brief clear RTC flag status
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\param[in] flag: specify which flag status to clear
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\arg RTC_FLAG_SECOND: second interrupt flag
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\arg RTC_FLAG_ALARM: alarm interrupt flag
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\arg RTC_FLAG_OVERFLOW: overflow interrupt flag
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\arg RTC_FLAG_RSYN: registers synchronized flag
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\param[out] none
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\retval none
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*/
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void rtc_flag_clear(uint32_t flag)
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{
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/* clear RTC flag */
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RTC_CTL &= ~flag;
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}
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