2021-08-20 16:37:50 +08:00
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/*
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2022-07-26 10:11:12 +08:00
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* Copyright (c) 2006-2022, RT-Thread Development Team
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2021-08-20 16:37:50 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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2021-08-27 15:19:21 +08:00
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* 2021-08-27 Jiao first version
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2021-08-20 16:37:50 +08:00
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*/
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2021-08-27 15:19:21 +08:00
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2021-08-20 16:37:50 +08:00
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#include "board.h"
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FL_ErrorStatus FL_UART_GPIO_Init(UART_Type *UARTx)
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{
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2021-08-27 15:19:21 +08:00
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FL_ErrorStatus status = FL_FAIL;
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FL_GPIO_InitTypeDef GPIO_InitStruct;
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if (UARTx == UART0)
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{
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GPIO_InitStruct.pin = FL_GPIO_PIN_13;
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GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
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GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
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GPIO_InitStruct.pull = FL_DISABLE;
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GPIO_InitStruct.remapPin = FL_DISABLE;
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status = FL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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GPIO_InitStruct.pin = FL_GPIO_PIN_14;
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GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
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GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
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GPIO_InitStruct.pull = FL_DISABLE;
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GPIO_InitStruct.remapPin = FL_DISABLE;
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status = FL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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}
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else if (UARTx == UART1)
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{
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GPIO_InitStruct.pin = FL_GPIO_PIN_13;
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GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
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GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
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GPIO_InitStruct.pull = FL_DISABLE;
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GPIO_InitStruct.remapPin = FL_DISABLE;
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status = FL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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GPIO_InitStruct.pin = FL_GPIO_PIN_14;
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GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
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GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
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GPIO_InitStruct.pull = FL_DISABLE;
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GPIO_InitStruct.remapPin = FL_DISABLE;
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status = FL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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}
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else if (UARTx == UART4)
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{
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GPIO_InitStruct.pin = FL_GPIO_PIN_0;
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GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
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GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
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GPIO_InitStruct.pull = FL_DISABLE;
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GPIO_InitStruct.remapPin = FL_DISABLE;
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status = FL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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GPIO_InitStruct.pin = FL_GPIO_PIN_1;
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GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
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GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
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GPIO_InitStruct.pull = FL_DISABLE;
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GPIO_InitStruct.remapPin = FL_DISABLE;
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status = FL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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}
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return status;
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2021-08-20 16:37:50 +08:00
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}
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2022-07-26 10:11:12 +08:00
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FL_ErrorStatus FL_SPI_GPIO_Init(SPI_Type *SPIx)
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{
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FL_ErrorStatus status = FL_FAIL;
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FL_GPIO_InitTypeDef GPIO_InitStruct;
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if (SPIx == SPI1)
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{
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GPIO_InitStruct.pin = FL_GPIO_PIN_11 | FL_GPIO_PIN_10 | FL_GPIO_PIN_9;
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GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
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GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
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GPIO_InitStruct.pull = FL_DISABLE;
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GPIO_InitStruct.remapPin = FL_DISABLE;
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2021-08-20 16:37:50 +08:00
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2022-07-26 10:11:12 +08:00
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status=FL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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}
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else if (SPIx == SPI2)
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{
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GPIO_InitStruct.pin = FL_GPIO_PIN_8 | FL_GPIO_PIN_10 | FL_GPIO_PIN_9;
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GPIO_InitStruct.mode = FL_GPIO_MODE_DIGITAL;
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GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
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GPIO_InitStruct.pull = FL_DISABLE;
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GPIO_InitStruct.remapPin = FL_DISABLE;
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status=FL_GPIO_Init(GPIOC, &GPIO_InitStruct);
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}
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return status;
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}
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2021-08-20 16:37:50 +08:00
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static void RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLL_R, uint32_t PLL_DB, uint32_t PLL_O)
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{
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MODIFY_REG(RCC->PLLCR, RCC_PLLCR_DB_Msk | RCC_PLLCR_REFPRSC_Msk | RCC_PLLCR_OSEL_Msk | RCC_PLLCR_INSEL_Msk,
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(PLL_DB << RCC_PLLCR_DB_Pos) | PLL_R | PLL_O | Source);
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}
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static void RCHFInit(uint32_t clock)
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{
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2021-08-27 15:19:21 +08:00
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switch (clock)
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2021-08-20 16:37:50 +08:00
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{
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2021-08-27 15:19:21 +08:00
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case FL_RCC_RCHF_FREQUENCY_8MHZ:
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FL_RCC_RCHF_WriteTrimValue(RCHF8M_TRIM);
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break;
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2021-08-20 16:37:50 +08:00
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2021-08-27 15:19:21 +08:00
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case FL_RCC_RCHF_FREQUENCY_16MHZ:
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FL_RCC_RCHF_WriteTrimValue(RCHF16M_TRIM);
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break;
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2021-08-20 16:37:50 +08:00
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2021-08-27 15:19:21 +08:00
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case FL_RCC_RCHF_FREQUENCY_24MHZ:
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FL_RCC_RCHF_WriteTrimValue(RCHF24M_TRIM);
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break;
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2021-08-20 16:37:50 +08:00
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2021-08-27 15:19:21 +08:00
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default:
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FL_RCC_RCHF_WriteTrimValue(RCHF8M_TRIM);
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break;
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2021-08-20 16:37:50 +08:00
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}
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FL_RCC_RCHF_SetFrequency(clock);
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}
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void SelRCHFToPLL(uint32_t rchf, uint32_t clock)
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{
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uint32_t div = FL_RCC_PLL_PSC_DIV8;
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2021-08-27 15:19:21 +08:00
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if (clock > 64)
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{
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return;
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}
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2021-08-20 16:37:50 +08:00
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RCHFInit(rchf);
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2021-08-27 15:19:21 +08:00
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switch (rchf)
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2021-08-20 16:37:50 +08:00
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{
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2021-08-27 15:19:21 +08:00
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case FL_RCC_RCHF_FREQUENCY_16MHZ:
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div = FL_RCC_PLL_PSC_DIV16;
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break;
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2021-08-20 16:37:50 +08:00
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2021-08-27 15:19:21 +08:00
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case FL_RCC_RCHF_FREQUENCY_24MHZ:
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div = FL_RCC_PLL_PSC_DIV24;
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break;
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2021-08-20 16:37:50 +08:00
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2021-08-27 15:19:21 +08:00
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default:
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break;
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2021-08-20 16:37:50 +08:00
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}
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2021-08-27 15:19:21 +08:00
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if (clock <= 24)
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2021-08-20 16:37:50 +08:00
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{
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FL_FLASH_SetReadWait(FLASH, FL_FLASH_READ_WAIT_0CYCLE);
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}
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else
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2021-08-27 15:19:21 +08:00
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{
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if ((clock > 24) && (clock <= 48))
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2021-08-20 16:37:50 +08:00
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{
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FL_FLASH_SetReadWait(FLASH, FL_FLASH_READ_WAIT_1CYCLE);
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}
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else
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{
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FL_FLASH_SetReadWait(FLASH, FL_FLASH_READ_WAIT_1CYCLE);
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}
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2021-08-27 15:19:21 +08:00
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}
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2021-08-20 16:37:50 +08:00
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RCC_PLL_ConfigDomain_SYS(FL_RCC_PLL_CLK_SOURCE_RCHF, div, clock, FL_RCC_PLL_OUTPUT_X1);
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FL_RCC_PLL_Enable();
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2021-08-27 15:19:21 +08:00
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while (FL_RCC_IsActiveFlag_PLLReady() != FL_SET);
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2021-08-20 16:37:50 +08:00
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FL_RCC_SetAHBPrescaler(FL_RCC_AHBCLK_PSC_DIV1);
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FL_RCC_SetAPB1Prescaler(FL_RCC_APB1CLK_PSC_DIV1);
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FL_RCC_SetAPB2Prescaler(FL_RCC_APB2CLK_PSC_DIV1);
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FL_RCC_SetSystemClockSource(FL_RCC_SYSTEM_CLK_SOURCE_PLL);
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}
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