447 lines
13 KiB
C
447 lines
13 KiB
C
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/**
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*********************************************************************************
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*
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* @file ald_dma.c
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* @brief DMA module driver.
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*
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* @version V1.0
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* @date 17 Feb. 2023
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* @author AE Team
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* @note
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* Change Logs:
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* Date Author Notes
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* 17 Feb. 2023 Lisq The first version
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*
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* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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**********************************************************************************
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*/
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#include <string.h>
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#include "ald_dma.h"
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/** @addtogroup ES32VF2264_ALD
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* @{
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*/
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/** @defgroup DMA DMA
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* @brief DMA module driver
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* @{
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*/
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/** @defgroup DMA_Private_Variables DMA Private Variables
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* @{
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*/
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ald_dma_call_back_t dma_cbk[7];
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/**
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* @}
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*/
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/** @defgroup DMA_Private_Functions DMA Private Functions
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* @{
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*/
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/**
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* @brief Configure DMA channel using dma_config_t structure
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* @param None
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* @param config: Pointer to dma_config_t which contains
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* DMA channel parameter. see @ref dma_config_t
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* @retval None
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*/
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void ald_dma_config_base(ald_dma_config_t *config)
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{
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assert_param(config->src != NULL);
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assert_param(config->dst != NULL);
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assert_param(IS_DMA_DATA_SIZE(config->size));
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assert_param(IS_DMA_DATASIZE_TYPE(config->src_data_width));
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assert_param(IS_DMA_DATASIZE_TYPE(config->dst_data_width));
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assert_param(IS_DMA_DATAINC_TYPE(config->src_inc));
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assert_param(IS_DMA_DATAINC_TYPE(config->dst_inc));
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assert_param(IS_DMA_ARBITERCONFIG_TYPE(config->R_power));
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assert_param(IS_DMA_PRIORITY_TYPE(config->priority));
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assert_param(IS_DMA_MSEL_TYPE(config->msel));
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assert_param(IS_DMA_MSIGSEL_TYPE(config->msigsel));
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assert_param(IS_DMA_CHANNEL(config->channel));
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WRITE_REG(DMA->CHANNEL[config->channel].SAR, (uint32_t)config->src);
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MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_SDWSEL_MSK, config->src_data_width << DMA_CON_SDWSEL_POSS);
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MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_SINC_MSK, config->src_inc << DMA_CON_SINC_POS);
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WRITE_REG(DMA->CHANNEL[config->channel].DAR, (uint32_t)config->dst);
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MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_DDWSEL_MSK, config->dst_data_width << DMA_CON_DDWSEL_POSS);
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MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_DINC_MSK, config->dst_inc << DMA_CON_DINC_POS);
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MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_CIRC_MSK, config->circle_mode << DMA_CON_CIRC_POS);
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MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_M2M_MSK, config->mem_to_mem << DMA_CON_M2M_POS);
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MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_CHPRI_MSK, config->priority << DMA_CON_CHPRI_POSS);
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MODIFY_REG(DMA->CHANNEL[config->channel].CON, DMA_CON_MAX_BURST_MSK, config->R_power << DMA_CON_MAX_BURST_POSS);
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MODIFY_REG(DMA->CHANNEL[config->channel].NDT, DMA_NDT_TNDT_MSK, config->size << DMA_NDT_TNDT_POSS);
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MODIFY_REG(DMA_MUX->CH_SELCON[config->channel], DMA_SELCON_MSEL_MSK, config->msel << DMA_SELCON_MSEL_POSS);
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MODIFY_REG(DMA_MUX->CH_SELCON[config->channel], DMA_SELCON_MSIGSEL_MSK, config->msigsel << DMA_SELCON_MSIGSEL_POSS);
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return;
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}
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/**
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* @brief Configure DMA channel according to the specified parameter
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* in the dma_handle_t structure. The DMA mode is basic.
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* This mode is used to carry data from peripheral to memory
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* or from memory to peripheral.
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* @param hperh: Pointer to dma_handle_t structure that contains
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* configuration information for specified DMA channel.
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* @retval None
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*/
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void ald_dma_config_basic(ald_dma_handle_t *hperh)
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{
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dma_cbk[hperh->config.channel].cplt_tc_cbk = hperh->cplt_tc_cbk;
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dma_cbk[hperh->config.channel].cplt_ht_cbk = hperh->cplt_ht_cbk;
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dma_cbk[hperh->config.channel].cplt_tc_arg = hperh->cplt_tc_arg;
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dma_cbk[hperh->config.channel].cplt_ht_arg = hperh->cplt_ht_arg;
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ald_dma_clear_flag_status(hperh->config.channel, ALD_DMA_IT_FLAG_TC);
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ald_dma_clear_flag_status(hperh->config.channel, ALD_DMA_IT_FLAG_HT);
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ald_dma_config_base(&hperh->config);
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ald_dma_channel_config(hperh->config.channel, ENABLE);
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return;
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}
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/**
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* @brief Configure DMA channel according to the specified parameter.
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* The DMA mode is basic. This mode is used to carry data
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* from peripheral to memory or negative direction. If user want
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* use the dma easily, they can invoke this function.
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* @param DMAx: Pointer to DMA peripheral
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* @param src: Source data begin pointer
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* @param dst: Destination data begin pointer
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* @param size: The total number of DMA transfers that DMA cycle contains
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* @param msel: Input source to DMA channel @ref dma_msel_t
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* @param msigsel: Input signal to DMA channel @ref dma_msigsel_t
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* @param channel: Channel index which will be used
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* @param cbk: DMA complete callback function
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*
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* @retval None
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*
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*/
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void ald_dma_config_basic_easy(void *src, void *dst, uint16_t size, ald_dma_msel_t msel,
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ald_dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg))
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{
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ald_dma_handle_t hperh;
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ald_dma_config_struct(&hperh.config);
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if (((uint32_t)src) >= 0x40000000)
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hperh.config.src_inc = ALD_DMA_DATA_INC_DISABLE;
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if (((uint32_t)dst) >= 0x40000000)
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hperh.config.dst_inc = ALD_DMA_DATA_INC_DISABLE;
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hperh.config.src = src;
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hperh.config.dst = dst;
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hperh.config.size = size;
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hperh.config.msel = msel;
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hperh.config.msigsel = msigsel;
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hperh.config.channel = channel;
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hperh.perh = DMA;
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hperh.cplt_tc_cbk = cbk;
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hperh.cplt_tc_arg = NULL;
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hperh.cplt_ht_cbk = NULL;
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ald_dma_clear_flag_status(channel, ALD_DMA_IT_FLAG_TC);
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ald_dma_clear_flag_status(channel, ALD_DMA_IT_FLAG_HT);
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ald_dma_config_basic(&hperh);
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return;
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}
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/**
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* @brief Handle DMA interrupt
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* @retval None
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*/
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void ald_dma_irq_handler(void)
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{
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uint8_t i;
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for (i = 0; i < ALD_DMA_CH_COUNT; ++i)
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{
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if (READ_BIT(DMA->IFM, 1U << (2U * i)))
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{
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if (dma_cbk[i].cplt_tc_cbk != NULL)
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dma_cbk[i].cplt_tc_cbk(dma_cbk[i].cplt_tc_arg);
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DMA->ICR = 1U << (2U * i);
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}
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if (READ_BIT(DMA->IFM, 1U << (2U * i + 1U)))
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{
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if (dma_cbk[i].cplt_ht_cbk != NULL)
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dma_cbk[i].cplt_ht_cbk(dma_cbk[i].cplt_ht_arg);
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DMA->ICR = 1U << (2U * i + 1U);
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}
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}
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return;
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}
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/**
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* @}
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*/
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/** @defgroup DMA_Public_Functions DMA Public Functions
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* @{
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*/
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/** @defgroup DMA_Public_Functions_Group1 Initialization functions
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* @brief Initialization functions
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*
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* @{
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*/
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/**
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* @brief Reset the DMA register
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* @param None
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* @retval None
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*/
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void ald_dma_reset(void)
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{
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uint32_t i;
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WRITE_REG(DMA->IDR, 0x3FFF);
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WRITE_REG(DMA->ICR, 0x3FFF);
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for (i = 0; i < DMA_CHANNELS; ++i)
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{
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CLEAR_BIT(DMA->CHANNEL[i].CON, DMA_CON_CHEN_MSK);
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WRITE_REG(DMA->CHANNEL[i].CON, 0x0);
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WRITE_REG(DMA->CHANNEL[i].SAR, 0x0);
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WRITE_REG(DMA->CHANNEL[i].DAR, 0x0);
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WRITE_REG(DMA->CHANNEL[i].NDT, 0x0);
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WRITE_REG(DMA_MUX->CH_SELCON[i], 0x0);
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}
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return;
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}
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/**
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* @brief DMA module initialization, this function
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* is invoked by ald_cmu_init().
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* @param None
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* @retval None
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*/
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void ald_dma_init(void)
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{
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memset(dma_cbk, 0x0, sizeof(dma_cbk));
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ald_dma_reset();
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ald_mcu_irq_config(DMA_IRQn, 4, ENABLE);
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return;
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}
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/**
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* @brief Configure dma_config_t structure using default parameter.
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* User can invoked this function, before configure dma_config_t
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* @param config: Pointer to dma_config_t structure, see @ref dma_config_t
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* @retval None
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*/
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void ald_dma_config_struct(ald_dma_config_t *config)
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{
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config->size = 0;
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config->src_data_width = ALD_DMA_DATA_SIZE_BYTE;
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config->dst_data_width = ALD_DMA_DATA_SIZE_BYTE;
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config->src_inc = ALD_DMA_DATA_INC_DISABLE;
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config->dst_inc = ALD_DMA_DATA_INC_DISABLE;
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config->R_power = ALD_DMA_R_POWER_1;
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config->priority = ALD_DMA_LOW_PRIORITY;
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config->mem_to_mem = DISABLE;
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config->circle_mode = DISABLE;
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config->msel = ALD_DMA_MSEL_NONE;
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config->msigsel = ALD_DMA_MSIGSEL_NONE;
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config->channel = ALD_DMA_CH_0;
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return;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @defgroup DMA_Public_Functions_Group2 DMA Control functions
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* @brief DMA control functions
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*
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* @verbatim
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===================================================================
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#### DMA control functions ####
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===================================================================
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[..]
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This subsection provides some functions allowing to control DMA:
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(+) ald_dma_channel_config(): Control DMA channel ENABLE/DISABLE.
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(+) ald_dma_interrupt_config(): Control DMA channel interrupt ENABLE or
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DISABLE.
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(+) ald_dma_get_it_status(): Check whether the specified channel
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interrupt is SET or RESET.
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(+) ald_dma_get_flag_status(): Check whether the specified channel
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flag is SET or RESET.
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(+) ald_dma_clear_flag_status(): Clear the specified channel
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pending flag
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@endverbatim
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* @{
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*/
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/**
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* @brief Configure channel enable or disable. It will unbind descriptor with
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* channel, when channel has been disable.
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* @param None
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* @param channel: channel index
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* @param state: status of channel:
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* @arg ENABLE: Enable the channel
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* @arg DISABLE: Disable the channel
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* @retval None
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*/
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void ald_dma_channel_config(uint8_t channel, type_func_t state)
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{
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assert_param(IS_DMA_CHANNEL(channel));
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assert_param(IS_FUNC_STATE(state));
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if (state)
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{
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SET_BIT(DMA->CHANNEL[channel].CON, DMA_CON_CHEN_MSK);
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}
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else
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{
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CLEAR_BIT(DMA->CHANNEL[channel].CON, DMA_CON_CHEN_MSK);
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WRITE_REG(DMA->CHANNEL[channel].CON, 0x0);
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WRITE_REG(DMA->CHANNEL[channel].SAR, 0x0);
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WRITE_REG(DMA->CHANNEL[channel].DAR, 0x0);
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WRITE_REG(DMA->CHANNEL[channel].NDT, 0x0);
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WRITE_REG(DMA_MUX->CH_SELCON[channel], 0x0);
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}
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return;
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}
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/**
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* @brief Configure the interrupt enable or disable
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* @param channel: Channel index.
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* @arg 0~6: Channel index
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* @param it: IT type.
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* @arg DMA_IT_FLAG_TC
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* @arg DMA_IT_FLAG_HT
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* @param state: status of channel:
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* @arg ENABLE: Enable the channel
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* @arg DISABLE: Disable the channel
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*
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* @retval None
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*/
|
||
|
|
void ald_dma_interrupt_config(uint8_t channel, ald_dma_it_flag_t it, type_func_t state)
|
||
|
|
{
|
||
|
|
assert_param(IS_DMA_CHANNEL(channel));
|
||
|
|
assert_param(IS_DMA_IT_TYPE(it));
|
||
|
|
assert_param(IS_FUNC_STATE(state));
|
||
|
|
|
||
|
|
if (state)
|
||
|
|
SET_BIT(DMA->IER, 1U << (channel * 2U + it));
|
||
|
|
else
|
||
|
|
SET_BIT(DMA->IDR, 1U << (channel * 2U + it));
|
||
|
|
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Check whether the specified channel interrupt
|
||
|
|
* is set or reset
|
||
|
|
* @param it: IT type.
|
||
|
|
* @arg DMA_IT_FLAG_TC
|
||
|
|
* @arg DMA_IT_FLAG_HT
|
||
|
|
* @param channel: Channel index
|
||
|
|
* @arg 0~6: Channel index
|
||
|
|
* @retval Status:
|
||
|
|
* - SET: Channel interrupt is set
|
||
|
|
* - RESET: Channel interrupt is reset
|
||
|
|
*/
|
||
|
|
it_status_t ald_dma_get_it_status(uint8_t channel, ald_dma_it_flag_t it)
|
||
|
|
{
|
||
|
|
assert_param(IS_DMA_CHANNEL(channel));
|
||
|
|
assert_param(IS_DMA_IT_TYPE(it));
|
||
|
|
|
||
|
|
if (READ_BIT(DMA->IVS, 1 << (channel * 2U + it)))
|
||
|
|
return SET;
|
||
|
|
|
||
|
|
return RESET;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Check whether the specified channel flag
|
||
|
|
* is set or reset
|
||
|
|
* @param channel: Channel index
|
||
|
|
* @arg 0~6: Channel index
|
||
|
|
* @param it: IT type.
|
||
|
|
* @arg DMA_IT_FLAG_TC
|
||
|
|
* @arg DMA_IT_FLAG_HT
|
||
|
|
* @retval Status:
|
||
|
|
* - SET: Channel flag is set
|
||
|
|
* - RESET: Channel flag is reset
|
||
|
|
*/
|
||
|
|
flag_status_t ald_dma_get_flag_status(uint8_t channel, ald_dma_it_flag_t it)
|
||
|
|
{
|
||
|
|
assert_param(IS_DMA_CHANNEL(channel));
|
||
|
|
assert_param(IS_DMA_IT_TYPE(it));
|
||
|
|
|
||
|
|
if (READ_BIT(DMA->IFM, 1 << (channel * 2U + it)))
|
||
|
|
return SET;
|
||
|
|
|
||
|
|
return RESET;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Clear the specified channel pending flag
|
||
|
|
* @param channel: Channel index
|
||
|
|
* @arg 0~6: Channel index
|
||
|
|
* @param it: IT type.
|
||
|
|
* @arg DMA_IT_FLAG_TC
|
||
|
|
* @arg DMA_IT_FLAG_HT
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void ald_dma_clear_flag_status(uint8_t channel, ald_dma_it_flag_t it)
|
||
|
|
{
|
||
|
|
assert_param(IS_DMA_CHANNEL(channel));
|
||
|
|
assert_param(IS_DMA_IT_TYPE(it));
|
||
|
|
|
||
|
|
SET_BIT(DMA->ICR, 1U << (channel * 2U + it));
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|