261 lines
7.6 KiB
ArmAsm
261 lines
7.6 KiB
ArmAsm
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;/*
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; * Copyright (c) 2006-2022, RT-Thread Development Team
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; *
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; * SPDX-License-Identifier: Apache-2.0
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2009-01-20 Bernard first version
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; * 2011-07-22 Bernard added thumb mode porting
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; * 2013-05-24 Grissiom port to CCS
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; * 2013-05-26 Grissiom optimize for ARMv7
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; * 2013-10-20 Grissiom port to GCC
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; * 2024-03-11 Wangyuqiang rzn2l adapt
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; */
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SECTION .text:CODE(2)
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ARM
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IMPORT rt_thread_switch_interrupt_flag
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IMPORT rt_interrupt_from_thread
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IMPORT rt_interrupt_to_thread
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IMPORT rt_interrupt_enter
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IMPORT rt_interrupt_leave
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IMPORT rt_hw_trap_irq
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;/*
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; * rt_base_t rt_hw_interrupt_disable();
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; */
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EXPORT rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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MRS r0, CPSR
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CPSID I
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BX lr
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;/*
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; * void rt_hw_interrupt_enable(rt_base_t level);
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; */
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EXPORT rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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MSR CPSR_c, r0
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BX lr
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;/*
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; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
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; * r0 --> from
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; * r1 --> to
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; */
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EXPORT rt_hw_context_switch
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rt_hw_context_switch:
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STMDB sp!, {lr} ; push pc (lr should be pushed in place of PC)
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STMDB sp!, {r0-r12, lr} ; push lr & register file
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MRS r4, CPSR
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TST lr, #0x01
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;ORRNE r4, r4, #0x20 ; it's thumb code
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CMP r4, #0
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BNE ne_label
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ne_label:
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ORR r4, r4, #0x20
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STMDB sp!, {r4} ; push cpsr
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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VMRS r4, fpexc
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TST r4, #0x40000000
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BEQ __no_vfp_frame1
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VSTMDB sp!, {d0-d15}
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VMRS r5, fpscr
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; TODO: add support for Common VFPv3.
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; Save registers like FPINST, FPINST2
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STMDB sp!, {r5}
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__no_vfp_frame1:
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STMDB sp!, {r4}
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#endif
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STR sp, [r0] ; store sp in preempted tasks TCB
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LDR sp, [r1] ; get new task stack pointer
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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LDMIA sp!, {r0} ;@ get fpexc
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VMSR fpexc, r0 ;@ restore fpexc
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TST r0, #0x40000000
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BEQ __no_vfp_frame2
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LDMIA sp!, {r1} ;@ get fpscr
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VMSR fpscr, r1
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VLDMIA sp!, {d0-d15}
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__no_vfp_frame2:
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#endif
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LDMIA sp!, {r4} ; pop new task cpsr to spsr
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MSR spsr_cxsf, r4
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LDMIA sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
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MOV lr, pc
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STMIA sp!, {lr}
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;/*
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; * void rt_hw_context_switch_to(rt_uint32 to)
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; * r0 --> to
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; */
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EXPORT rt_hw_context_switch_to
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rt_hw_context_switch_to:
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LDR sp, [r0] ; get new task stack pointer
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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LDMIA sp!, {r0} @ get fpexc
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VMSR fpexc, r0
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TST r0, #0x40000000
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BEQ __no_vfp_frame_to
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LDMIA sp!, {r1} @ get fpscr
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VMSR fpscr, r1
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VLDMIA sp!, {d0-d15}
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__no_vfp_frame_to:
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#endif
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LDMIA sp!, {r4} ; pop new task cpsr to spsr
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MSR spsr_cxsf, r4
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LDMIA sp!, {r0-r12, lr, pc}^
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;/*
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; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)@
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; */
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EXPORT rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt:
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LDR r2, =rt_thread_switch_interrupt_flag
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LDR r3, [r2]
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CMP r3, #1
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BEQ _reswitch
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MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1
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STR r3, [r2]
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LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
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STR r0, [r2]
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_reswitch:
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LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
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STR r1, [r2]
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BX lr
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EXPORT IRQ_Handler
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IRQ_Handler:
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STMDB sp!, {r0-r12,lr}
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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VMRS r0, fpexc
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TST r0, #0x40000000
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BEQ __no_vfp_frame_str_irq
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VSTMDB sp!, {d0-d15}
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VMRS r1, fpscr
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; TODO: add support for Common VFPv3.
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; Save registers like FPINST, FPINST2
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STMDB sp!, {r1}
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__no_vfp_frame_str_irq:
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STMDB sp!, {r0}
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#endif
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BL rt_interrupt_enter
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BL rt_hw_trap_irq
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BL rt_interrupt_leave
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; if rt_thread_switch_interrupt_flag set, jump to
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; rt_hw_context_switch_interrupt_do and don't return
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LDR r0, =rt_thread_switch_interrupt_flag
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LDR r1, [r0]
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CMP r1, #1
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BEQ rt_hw_context_switch_interrupt_do
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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LDMIA sp!, {r0} ; get fpexc
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VMSR fpexc, r0
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TST r0, #0x40000000
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BEQ __no_vfp_frame_ldr_irq
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LDMIA sp!, {r1} ; get fpscr
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VMSR fpscr, r1
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VLDMIA sp!, {d0-d15}
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__no_vfp_frame_ldr_irq:
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#endif
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LDMIA sp!, {r0-r12,lr}
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SUBS pc, lr, #4
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;/*
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; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
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; */
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EXPORT rt_hw_context_switch_interrupt_do
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rt_hw_context_switch_interrupt_do:
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MOV r1, #0 ; clear flag
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STR r1, [r0]
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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LDMIA sp!, {r0} ; get fpexc
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VMSR fpexc, r0
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TST r0, #0x40000000
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BEQ __no_vfp_frame_do1
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LDMIA sp!, {r1} ; get fpscr
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VMSR fpscr, r1
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VLDMIA sp!, {d0-d15}
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__no_vfp_frame_do1:
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#endif
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LDMIA sp!, {r0-r12,lr} ; reload saved registers
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STMDB sp, {r0-r3} ; save r0-r3. We will restore r0-r3 in the SVC
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; mode so there is no need to update SP.
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SUB r1, sp, #16 ; save the right SP value in r1, so we could restore r0-r3.
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SUB r2, lr, #4 ; save old task's pc to r2
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MRS r3, spsr ; get cpsr of interrupt thread
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; switch to SVC mode and no interrupt
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CPSID IF, #0x13
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STMDB sp!, {r2} ; push old task's pc
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STMDB sp!, {r4-r12,lr} ; push old task's lr,r12-r4
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LDMIA r1!, {r4-r7} ; restore r0-r3 of the interrupted thread
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STMDB sp!, {r4-r7} ; push old task's r3-r0. We don't need to push/pop them to
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; r0-r3 because we just want to transfer the data and don't
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; use them here.
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STMDB sp!, {r3} ; push old task's cpsr
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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VMRS r0, fpexc
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TST r0, #0x40000000
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BEQ __no_vfp_frame_do2
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VSTMDB sp!, {d0-d15}
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VMRS r1, fpscr
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; TODO: add support for Common VFPv3.
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; Save registers like FPINST, FPINST2
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STMDB sp!, {r1}
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__no_vfp_frame_do2:
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STMDB sp!, {r0}
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#endif
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LDR r4, =rt_interrupt_from_thread
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LDR r5, [r4]
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STR sp, [r5] ; store sp in preempted tasks's TCB
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LDR r6, =rt_interrupt_to_thread
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LDR r6, [r6]
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LDR sp, [r6] ; get new task's stack pointer
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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LDMIA sp!, {r0} ; get fpexc
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VMSR fpexc, r0
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TST r0, #0x40000000
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BEQ __no_vfp_frame_do3
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LDMIA sp!, {r1} ; get fpscr
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VMSR fpscr, r1
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VLDMIA sp!, {d0-d15}
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__no_vfp_frame_do3:
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#endif
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LDMIA sp!, {r4} ; pop new task's cpsr to spsr
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MSR spsr_cxsf, r4
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LDMIA sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr
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MOV lr, pc
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STMIA sp!, {r0-r12, lr}
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STR pc, [sp]
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END
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