271 lines
6.9 KiB
C
271 lines
6.9 KiB
C
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-3-30 bluebear233 first version
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*/
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#include "NuMicro.h"
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#include <rtdevice.h>
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#ifdef RT_USING_SPI
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/* Private Define ---------------------------------------------------------------*/
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#define USEING_QSPI0
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/* Private Typedef --------------------------------------------------------------*/
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struct m487_qspi
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{
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struct rt_spi_bus dev;
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struct rt_spi_configuration configuration;
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QSPI_T *spi_base;
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rt_uint8_t init_gpio:1;
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};
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/* Private functions ------------------------------------------------------------*/
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static rt_err_t m487_qspi_bus_configure(struct rt_spi_device *device,
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struct rt_spi_configuration *configuration);
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static rt_uint32_t m487_qspi_bus_xfer(struct rt_spi_device *device,
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struct rt_spi_message *message);
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/* Private Variables ------------------------------------------------------------*/
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struct rt_spi_ops m487_spi_poll_ops =
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{
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.configure = m487_qspi_bus_configure,
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.xfer = m487_qspi_bus_xfer,
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};
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#ifdef USEING_QSPI0
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static struct m487_qspi qspi0 =
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{
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.spi_base = QSPI0,
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};
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#endif
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static rt_err_t m487_qspi_bus_configure(struct rt_spi_device *device,
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struct rt_spi_configuration *configuration) {
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struct m487_qspi *spi;
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uint32_t u32QSPIMode;
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uint32_t u32BusClock;
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rt_uint8_t init_bus;
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spi = (struct m487_qspi *) device->bus;
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init_bus = 0;
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if (!spi->init_gpio)
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{
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spi->init_gpio = 1;
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init_bus = 1;
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if(spi->spi_base == QSPI0)
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{
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/* Select PCLK0 as the clock source of QSPI0 */
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CLK_SetModuleClock(QSPI0_MODULE, CLK_CLKSEL2_QSPI0SEL_PLL,
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MODULE_NoMsk);
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/* Enable QSPI0 peripheral clock */
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CLK_EnableModuleClock(QSPI0_MODULE);
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/* Setup QSPI0 multi-function pins */
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SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC0MFP_Msk | SYS_GPC_MFPL_PC1MFP_Msk
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| SYS_GPC_MFPL_PC2MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk);
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SYS->GPC_MFPL |= SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0 | SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0
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| SYS_GPC_MFPL_PC2MFP_QSPI0_CLK | SYS_GPC_MFPL_PC3MFP_QSPI0_SS;
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/* Enable SPI0 clock pin (PC2) schmitt trigger */
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PC->SMTEN |= GPIO_SMTEN_SMTEN2_Msk;
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}
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}
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if(rt_memcmp(configuration, &spi->configuration, sizeof(*configuration)) != 0)
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{
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rt_memcpy(&spi->configuration, configuration, sizeof(*configuration));
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init_bus = 1;
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}
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if(init_bus)
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{
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switch(configuration->mode & RT_SPI_MODE_3)
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{
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case RT_SPI_MODE_0:u32QSPIMode = QSPI_MODE_0;break;
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case RT_SPI_MODE_1:u32QSPIMode = QSPI_MODE_1;break;
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case RT_SPI_MODE_2:u32QSPIMode = QSPI_MODE_2;break;
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case RT_SPI_MODE_3:u32QSPIMode = QSPI_MODE_3;break;
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default:RT_ASSERT(0);
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}
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u32BusClock = configuration->max_hz;
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if(u32BusClock > 50*1000*1000)
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{
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u32BusClock = 50*1000*1000;
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}
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QSPI_Open(spi->spi_base, QSPI_MASTER, u32QSPIMode, configuration->data_width, u32BusClock);
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QSPI_EnableAutoSS(spi->spi_base, QSPI_SS, QSPI_SS_ACTIVE_LOW);
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if(configuration->mode & RT_SPI_MSB)
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{
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QSPI_SET_MSB_FIRST(spi->spi_base);
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}
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else
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{
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QSPI_SET_LSB_FIRST(spi->spi_base);
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}
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}
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return RT_EOK;
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}
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/**
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* @brief SPI bus 轮询
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* @param dev : SPI总线设备结构体指针
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* @param send_addr : 发送缓冲区地址
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* @param recv_addr : 接收缓冲区地址
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* @param length : 数据长度
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*/
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static void qspi_transmission_with_poll(struct m487_qspi *spi_bus,
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const uint8_t *send_addr, uint8_t *recv_addr, int length)
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{
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QSPI_T *spi_base = spi_bus->spi_base;
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// 写
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if (send_addr != RT_NULL && recv_addr == RT_NULL)
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{
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while (length--)
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{
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// 等待TX FIFO 为空
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while(QSPI_GET_TX_FIFO_FULL_FLAG(spi_base));
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// 输入数据
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QSPI_WRITE_TX(spi_base, *send_addr++);
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}
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// 等待SPI空闲
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while(QSPI_IS_BUSY(spi_base));
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}
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// 读写
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else if (send_addr != RT_NULL && recv_addr != RT_NULL)
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{
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// 清空读FIFO
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if(!QSPI_GET_RX_FIFO_EMPTY_FLAG(spi_base))
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{
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QSPI_ClearRxFIFO(spi_base);
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while(!QSPI_GET_RX_FIFO_EMPTY_FLAG(spi_base));
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}
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while (length--)
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{
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// 等待TX FIFO 为空
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while(QSPI_GET_TX_FIFO_FULL_FLAG(spi_base));
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// 输入数据
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QSPI_WRITE_TX(spi_base, *send_addr++);
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// 读取RX FIFO
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while(!QSPI_GET_RX_FIFO_EMPTY_FLAG(spi_base))
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{
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*recv_addr++ = QSPI_READ_RX(spi_base);
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}
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}
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// 等待SPI空闲
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while(QSPI_IS_BUSY(spi_base))
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{
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while(!QSPI_GET_RX_FIFO_EMPTY_FLAG(spi_base))
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{
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*recv_addr++ = QSPI_READ_RX(spi_base);
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}
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}
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}
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//读
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else
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{
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// 清空读FIFO
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if(!QSPI_GET_RX_FIFO_EMPTY_FLAG(spi_base))
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{
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QSPI_ClearRxFIFO(spi_base);
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while(!QSPI_GET_RX_FIFO_EMPTY_FLAG(spi_base));
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}
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while (length--)
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{
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// 等待TX FIFO 为空
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while(QSPI_GET_TX_FIFO_FULL_FLAG(spi_base));
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// 输入数据
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QSPI_WRITE_TX(spi_base, 0x00);
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// 读取RX FIFO
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while(!QSPI_GET_RX_FIFO_EMPTY_FLAG(spi_base))
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{
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*recv_addr++ = QSPI_READ_RX(spi_base);
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}
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}
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// 等待SPI空闲
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while(QSPI_IS_BUSY(spi_base))
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{
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while(!QSPI_GET_RX_FIFO_EMPTY_FLAG(spi_base))
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{
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*recv_addr++ = QSPI_READ_RX(spi_base);
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}
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}
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while(!QSPI_GET_RX_FIFO_EMPTY_FLAG(spi_base))
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{
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*recv_addr++ = QSPI_READ_RX(spi_base);
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}
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}
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}
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static rt_uint32_t m487_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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struct m487_qspi *spi;
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spi = (struct m487_qspi *) device->bus;
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if (message->cs_take)
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{
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QSPI_SET_SS_LOW(spi->spi_base);
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}
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if (message->length > 0)
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{
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qspi_transmission_with_poll(spi, message->send_buf,
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message->recv_buf, message->length);
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}
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if (message->cs_release)
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{
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QSPI_SET_SS_HIGH(spi->spi_base);
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}
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return message->length;
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}
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static int m487_qspi_register_bus(struct m487_qspi *spi_bus, const char *name)
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{
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return rt_spi_bus_register(&spi_bus->dev, name, &m487_spi_poll_ops);
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}
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/**
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* 硬件QSPI注册
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*/
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static int rt_hw_qspi_init(void)
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{
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#ifdef USEING_QSPI0
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m487_qspi_register_bus(&qspi0, "qspi0");
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#endif
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return 0;
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}
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INIT_DEVICE_EXPORT(rt_hw_qspi_init);
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#endif
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