2017-11-01 13:30:17 +08:00
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/*
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2021-03-27 17:51:56 +08:00
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* Copyright (c) 2006-2021, RT-Thread Development Team
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2017-11-01 13:30:17 +08:00
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*
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2018-10-15 01:35:07 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2017-11-01 13:30:17 +08:00
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-20 Bernard first version
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*/
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2022-12-03 12:07:44 +08:00
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#include <backtrace.h>
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2023-01-09 10:08:55 +08:00
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#include <board.h>
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#include <rthw.h>
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#include <rtthread.h>
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2017-11-01 13:30:17 +08:00
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2019-03-25 20:03:49 +08:00
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#include "interrupt.h"
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2023-01-09 10:08:55 +08:00
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#include "mm_fault.h"
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2017-11-01 13:30:17 +08:00
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2022-12-03 12:07:44 +08:00
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#ifdef RT_USING_FINSH
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2017-11-01 13:30:17 +08:00
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extern long list_thread(void);
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#endif
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2022-12-16 18:38:28 +08:00
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#ifdef RT_USING_SMART
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2022-12-03 12:07:44 +08:00
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#include <lwp.h>
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#include <lwp_arch.h>
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2022-04-24 01:03:54 +08:00
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2022-12-03 12:07:44 +08:00
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#ifdef LWP_USING_CORE_DUMP
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#include <lwp_core_dump.h>
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#endif
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void check_user_fault(struct rt_hw_exp_stack *regs, uint32_t pc_adj, char *info)
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2022-04-24 01:03:54 +08:00
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{
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2022-12-03 12:07:44 +08:00
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uint32_t mode = regs->cpsr;
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if ((mode & 0x1f) == 0x10)
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{
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rt_kprintf("%s! pc = 0x%08x\n", info, regs->pc - pc_adj);
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#ifdef LWP_USING_CORE_DUMP
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lwp_core_dump(regs, pc_adj);
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#endif
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2023-09-09 09:35:56 +08:00
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sys_exit_group(-1);
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2022-12-03 12:07:44 +08:00
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}
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2022-04-24 01:03:54 +08:00
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}
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2022-12-03 12:07:44 +08:00
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int check_user_stack(struct rt_hw_exp_stack *regs)
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{
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2023-01-09 10:08:55 +08:00
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void *dfar = RT_NULL;
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2023-08-16 15:38:59 +08:00
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struct rt_lwp *lwp;
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2023-01-09 10:08:55 +08:00
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asm volatile("MRC p15, 0, %0, c6, c0, 0" : "=r"(dfar));
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2022-12-03 12:07:44 +08:00
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2023-01-09 10:08:55 +08:00
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if ((dfar >= (void *)USER_STACK_VSTART) && (dfar < (void *)USER_STACK_VEND))
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2022-12-03 12:07:44 +08:00
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{
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2023-03-30 08:25:15 +08:00
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struct rt_aspace_fault_msg msg = {
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2023-01-09 10:08:55 +08:00
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.fault_op = MM_FAULT_OP_WRITE,
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.fault_type = MM_FAULT_TYPE_PAGE_FAULT,
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2023-03-30 08:25:15 +08:00
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.fault_vaddr = dfar,
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2023-01-09 10:08:55 +08:00
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};
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2023-08-16 15:38:59 +08:00
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lwp = lwp_self();
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if (lwp && rt_aspace_fault_try_fix(lwp->aspace, &msg))
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2023-01-09 10:08:55 +08:00
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{
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regs->pc -= 8;
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return 1;
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}
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2022-12-03 12:07:44 +08:00
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}
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2023-01-09 10:08:55 +08:00
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2022-12-03 12:07:44 +08:00
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return 0;
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}
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#endif
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2017-11-01 13:30:17 +08:00
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/**
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* this function will show registers of CPU
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*
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* @param regs the registers point
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*/
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void rt_hw_show_register(struct rt_hw_exp_stack *regs)
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{
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rt_kprintf("Execption:\n");
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rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
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rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
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rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
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rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
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rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
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rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
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2022-12-16 18:38:28 +08:00
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#ifdef RT_USING_SMART
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2022-04-24 01:03:54 +08:00
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{
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2022-12-03 12:07:44 +08:00
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uint32_t v;
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asm volatile ("MRC p15, 0, %0, c5, c0, 0":"=r"(v));
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rt_kprintf("dfsr:0x%08x\n", v);
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asm volatile ("MRC p15, 0, %0, c2, c0, 0":"=r"(v));
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rt_kprintf("ttbr0:0x%08x\n", v);
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asm volatile ("MRC p15, 0, %0, c6, c0, 0":"=r"(v));
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rt_kprintf("dfar:0x%08x\n", v);
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2023-01-09 10:08:55 +08:00
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rt_kprintf("0x%08x -> 0x%08x\n", v, rt_kmem_v2p((void *)v));
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2022-04-24 01:03:54 +08:00
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}
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2022-12-03 12:07:44 +08:00
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#endif
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2021-07-05 14:43:33 +08:00
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}
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2017-11-01 13:30:17 +08:00
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/**
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* When comes across an instruction which it cannot handle,
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* it takes the undefined instruction trap.
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*
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* @param regs system registers
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*
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* @note never invoke this function in application
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*/
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2022-12-03 12:07:44 +08:00
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#ifdef RT_USING_FPU
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void set_fpexc(rt_uint32_t val);
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#endif
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2017-11-01 13:30:17 +08:00
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void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
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{
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2019-05-29 08:26:08 +08:00
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#ifdef RT_USING_FPU
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{
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2022-12-03 12:07:44 +08:00
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uint32_t ins;
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2019-05-29 08:26:08 +08:00
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uint32_t addr;
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if (regs->cpsr & (1 << 5))
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{
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/* thumb mode */
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addr = regs->pc - 2;
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2022-12-03 12:07:44 +08:00
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ins = (uint32_t)*(uint16_t *)addr;
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if ((ins & (3 << 11)) != 0)
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{
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/* 32 bit ins */
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ins <<= 16;
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ins += *(uint16_t *)(addr + 2);
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}
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2019-05-29 08:26:08 +08:00
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}
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else
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{
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addr = regs->pc - 4;
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2022-12-03 12:07:44 +08:00
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ins = *(uint32_t *)addr;
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2019-05-29 08:26:08 +08:00
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}
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2022-12-03 12:07:44 +08:00
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if ((ins & 0xe00) == 0xa00)
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2019-05-29 08:26:08 +08:00
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{
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/* float ins */
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2022-12-03 12:07:44 +08:00
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set_fpexc(1U << 30);
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2019-05-29 08:26:08 +08:00
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regs->pc = addr;
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return;
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}
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}
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#endif
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2022-12-16 18:38:28 +08:00
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#ifdef RT_USING_SMART
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2022-12-03 12:07:44 +08:00
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check_user_fault(regs, 4, "User undefined instruction");
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2017-11-01 13:30:17 +08:00
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#endif
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2022-12-03 12:07:44 +08:00
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rt_unwind(regs, 4);
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rt_kprintf("undefined instruction:\n");
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rt_hw_show_register(regs);
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#ifdef RT_USING_FINSH
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list_thread();
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#endif
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rt_hw_cpu_shutdown();
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2017-11-01 13:30:17 +08:00
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}
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/**
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* The software interrupt instruction (SWI) is used for entering
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* Supervisor mode, usually to request a particular supervisor
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* function.
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*
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* @param regs system registers
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*
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* @note never invoke this function in application
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*/
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void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
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{
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2022-12-03 12:07:44 +08:00
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rt_kprintf("software interrupt:\n");
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rt_hw_show_register(regs);
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#ifdef RT_USING_FINSH
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list_thread();
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2017-11-01 13:30:17 +08:00
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#endif
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2022-12-03 12:07:44 +08:00
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rt_hw_cpu_shutdown();
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2017-11-01 13:30:17 +08:00
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}
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/**
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* An abort indicates that the current memory access cannot be completed,
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* which occurs during an instruction prefetch.
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*
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* @param regs system registers
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*
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* @note never invoke this function in application
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*/
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void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
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{
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2022-12-16 18:38:28 +08:00
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#ifdef RT_USING_SMART
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2022-12-03 12:07:44 +08:00
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if (dbg_check_event(regs, 4))
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2021-07-05 14:43:33 +08:00
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{
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2022-12-03 12:07:44 +08:00
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return;
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2021-07-05 14:43:33 +08:00
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}
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2022-12-03 12:07:44 +08:00
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check_user_fault(regs, 4, "User prefetch abort");
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#endif
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rt_unwind(regs, 4);
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rt_kprintf("prefetch abort:\n");
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rt_hw_show_register(regs);
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#ifdef RT_USING_FINSH
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list_thread();
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#endif
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rt_hw_cpu_shutdown();
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2017-11-01 13:30:17 +08:00
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}
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/**
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* An abort indicates that the current memory access cannot be completed,
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* which occurs during a data access.
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*
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* @param regs system registers
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*
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* @note never invoke this function in application
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*/
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void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
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{
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2022-12-16 18:38:28 +08:00
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#ifdef RT_USING_SMART
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2022-12-03 12:07:44 +08:00
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if (dbg_check_event(regs, 8))
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2021-07-05 14:43:33 +08:00
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{
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2022-12-03 12:07:44 +08:00
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return;
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2021-07-05 14:43:33 +08:00
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}
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2022-12-03 12:07:44 +08:00
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if (check_user_stack(regs))
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2021-07-05 14:43:33 +08:00
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{
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2022-12-03 12:07:44 +08:00
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return;
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2021-07-05 14:43:33 +08:00
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}
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2022-12-03 12:07:44 +08:00
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check_user_fault(regs, 8, "User data abort");
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#endif
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rt_unwind(regs, 8);
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rt_kprintf("data abort:");
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rt_hw_show_register(regs);
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#ifdef RT_USING_FINSH
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list_thread();
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#endif
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rt_hw_cpu_shutdown();
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2017-11-01 13:30:17 +08:00
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}
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/**
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* Normally, system will never reach here
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*
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* @param regs system registers
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*
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* @note never invoke this function in application
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*/
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void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
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{
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2022-12-03 12:07:44 +08:00
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rt_kprintf("reserved trap:\n");
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rt_hw_show_register(regs);
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#ifdef RT_USING_FINSH
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list_thread();
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2017-11-01 13:30:17 +08:00
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#endif
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2022-12-03 12:07:44 +08:00
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rt_hw_cpu_shutdown();
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2017-11-01 13:30:17 +08:00
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}
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void rt_hw_trap_irq(void)
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{
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2022-12-03 12:07:44 +08:00
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#ifdef SOC_BCM283x
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extern rt_uint8_t core_timer_flag;
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2017-11-01 13:30:17 +08:00
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void *param;
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2022-12-03 12:07:44 +08:00
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uint32_t irq;
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2017-11-01 13:30:17 +08:00
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rt_isr_handler_t isr_func;
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extern struct rt_irq_desc isr_table[];
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2022-12-03 12:07:44 +08:00
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uint32_t value = 0;
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value = IRQ_PEND_BASIC & 0x3ff;
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2017-11-01 13:30:17 +08:00
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2022-12-03 12:07:44 +08:00
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if(core_timer_flag != 0)
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{
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uint32_t cpu_id = rt_hw_cpu_id();
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uint32_t int_source = CORE_IRQSOURCE(cpu_id);
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if (int_source & 0x0f)
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{
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if (int_source & 0x08)
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{
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isr_func = isr_table[IRQ_ARM_TIMER].handler;
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#ifdef RT_USING_INTERRUPT_INFO
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isr_table[IRQ_ARM_TIMER].counter++;
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#endif
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if (isr_func)
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{
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param = isr_table[IRQ_ARM_TIMER].param;
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isr_func(IRQ_ARM_TIMER, param);
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}
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}
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}
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}
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2017-11-01 13:30:17 +08:00
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2022-12-03 12:07:44 +08:00
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/* local interrupt*/
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if (value)
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{
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if (value & (1 << 8))
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{
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value = IRQ_PEND1;
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irq = __rt_ffs(value) - 1;
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}
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else if (value & (1 << 9))
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{
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value = IRQ_PEND2;
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irq = __rt_ffs(value) + 31;
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}
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else
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{
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value &= 0x0f;
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irq = __rt_ffs(value) + 63;
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}
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/* get interrupt service routine */
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isr_func = isr_table[irq].handler;
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#ifdef RT_USING_INTERRUPT_INFO
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isr_table[irq].counter++;
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#endif
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if (isr_func)
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{
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/* Interrupt for myself. */
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param = isr_table[irq].param;
|
|
|
|
/* turn to interrupt service routine */
|
|
|
|
isr_func(irq, param);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
void *param;
|
|
|
|
int ir, ir_real;
|
|
|
|
rt_isr_handler_t isr_func;
|
|
|
|
extern struct rt_irq_desc isr_table[];
|
|
|
|
|
|
|
|
ir = rt_hw_interrupt_get_irq();
|
|
|
|
|
|
|
|
ir_real = ir & 0x3ff;
|
2019-03-25 20:03:49 +08:00
|
|
|
if (ir == 1023)
|
2017-11-01 13:30:17 +08:00
|
|
|
{
|
2019-03-25 20:03:49 +08:00
|
|
|
/* Spurious interrupt */
|
|
|
|
return;
|
2017-11-01 13:30:17 +08:00
|
|
|
}
|
|
|
|
|
2019-03-25 20:03:49 +08:00
|
|
|
/* get interrupt service routine */
|
2022-12-03 12:07:44 +08:00
|
|
|
isr_func = isr_table[ir_real].handler;
|
2017-11-01 13:30:17 +08:00
|
|
|
#ifdef RT_USING_INTERRUPT_INFO
|
2022-12-03 12:07:44 +08:00
|
|
|
isr_table[ir_real].counter++;
|
2017-11-01 13:30:17 +08:00
|
|
|
#endif
|
2019-03-25 20:03:49 +08:00
|
|
|
if (isr_func)
|
|
|
|
{
|
|
|
|
/* Interrupt for myself. */
|
2022-12-03 12:07:44 +08:00
|
|
|
param = isr_table[ir_real].param;
|
2019-03-25 20:03:49 +08:00
|
|
|
/* turn to interrupt service routine */
|
|
|
|
isr_func(ir, param);
|
2017-11-01 13:30:17 +08:00
|
|
|
}
|
2019-03-25 20:03:49 +08:00
|
|
|
|
|
|
|
/* end of interrupt */
|
2022-12-03 12:07:44 +08:00
|
|
|
rt_hw_interrupt_ack(ir);
|
|
|
|
#endif
|
2017-11-01 13:30:17 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void rt_hw_trap_fiq(void)
|
|
|
|
{
|
2019-03-25 20:03:49 +08:00
|
|
|
void *param;
|
|
|
|
int ir;
|
|
|
|
rt_isr_handler_t isr_func;
|
|
|
|
extern struct rt_irq_desc isr_table[];
|
|
|
|
|
|
|
|
ir = rt_hw_interrupt_get_irq();
|
|
|
|
|
|
|
|
/* get interrupt service routine */
|
|
|
|
isr_func = isr_table[ir].handler;
|
|
|
|
param = isr_table[ir].param;
|
|
|
|
|
|
|
|
/* turn to interrupt service routine */
|
|
|
|
isr_func(ir, param);
|
|
|
|
|
|
|
|
/* end of interrupt */
|
|
|
|
rt_hw_interrupt_ack(ir);
|
2017-11-01 13:30:17 +08:00
|
|
|
}
|
2019-03-25 20:03:49 +08:00
|
|
|
|