2022-09-15 17:08:26 +08:00
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/*
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2023-02-11 08:13:40 +08:00
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* Copyright (c) 2006-2023, RT-Thread Development Team
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2022-09-15 17:08:26 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-09-14 xjy198903 the first version for 1170
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*/
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#include <rtthread.h>
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#ifdef BSP_USING_FLEXSPI
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#include "board.h"
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#include <rtdevice.h>
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#ifdef RT_USING_FINSH
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#include <finsh.h>
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#endif
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#include "flexspi_port.h"
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#include "fsl_flexspi.h"
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#define COMBINATION_MODE 1U
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#define FREE_RUNNING_MODE 1U
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#define FLEXSPI_DEBUG
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#define LOG_TAG "drv.flexspi"
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#include <drv_log.h>
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static flexspi_device_config_t deviceconfig = {
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.flexspiRootClk = 12000000,
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.flashSize = FLASH_SIZE,
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.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
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.CSInterval = 2,
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.CSHoldTime = 3,
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.CSSetupTime = 3,
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.dataValidTime = 0,
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.columnspace = 0,
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.enableWordAddress = 0,
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.AWRSeqIndex = AWR_SEQ_INDEX,
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.AWRSeqNumber = AWR_SEQ_NUMBER,
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.ARDSeqIndex = ARD_SEQ_INDEX,
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.ARDSeqNumber = ARD_SEQ_NUMBER,
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.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
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.AHBWriteWaitInterval = 0,
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};
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const uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
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/* 8bit mode */
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[4 * ARD_SEQ_INDEX] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0),
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};
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static void flexspi_clock_init(clock_root_t root, uint8_t src, uint8_t div)
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{
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/*Clock setting for flexspi1*/
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CLOCK_SetRootClockDiv(root, div);
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CLOCK_SetRootClockMux(root, src);
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}
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static int rt_hw_imxrt_flexspi_init(void)
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{
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flexspi_config_t config;
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FLEXSPI_Type *base;
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#ifdef BSP_USING_FLEXSPI1
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base = FLEXSPI1_CONTROL_BASE;
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#else
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base = FLEXSPI2_CONTROL_BASE;
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#endif
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//Set root clk 80MHz
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flexspi_clock_init(kCLOCK_Root_Flexspi1, CLOCK_SRC, CLOCK_DIV);
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/*Get FLEXSPI default settings and configure the flexspi. */
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FLEXSPI_GetDefaultConfig(&config);
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/*Set AHB buffer size for reading data through AHB bus. */
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config.ahbConfig.enableAHBPrefetch = true;
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config.ahbConfig.enableAHBBufferable = true;
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config.ahbConfig.enableReadAddressOpt = true;
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config.ahbConfig.enableAHBCachable = true;
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2022-11-18 01:05:04 +08:00
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config.ahbConfig.enableClearAHBBufferOpt = true;
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2022-09-15 17:08:26 +08:00
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config.rxSampleClock = FLEXSPI_RX_SAMPLE_CLOCK;
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if(COMBINATION_MODE)
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{
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config.enableCombination = true;
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}
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if(FREE_RUNNING_MODE)
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{
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config.enableSckFreeRunning = true;
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}
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FLEXSPI_Init(base, &config);
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/* Configure flash settings according to serial flash feature. */
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FLEXSPI_SetFlashConfig(base, &deviceconfig, FLASH_PORT);
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/* Update LUT table. */
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FLEXSPI_UpdateLUT(base, 0, customLUT, CUSTOM_LUT_LENGTH);
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/* Do software reset. */
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FLEXSPI_SoftwareReset(base);
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return 0;
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}
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INIT_DEVICE_EXPORT(rt_hw_imxrt_flexspi_init);
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#ifdef FLEXSPI_DEBUG
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#ifdef FINSH_USING_MSH
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#define FLEXSPI_DATALEN 4U
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static rt_uint32_t send_buf[FLEXSPI_DATALEN] = {0x11223344, 0x55667788, 0x12345678, 0x9900aabb};
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static uint32_t recv_buf[FLEXSPI_DATALEN];
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/* read write 32bit test */
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static void flexspi_test(void)
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{
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volatile rt_uint32_t *flexspi = (rt_uint32_t *)FLEXSPI1_AHB_DATA_ADDRESS; /* FLEXSPI1 start address. */
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LOG_D("FLEXSPI Memory 32 bit Write Start\n");
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*(flexspi + 15) = send_buf[3];
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*(flexspi + 8) = send_buf[1];
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*(flexspi + 11) = send_buf[2];
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*(flexspi + 3) = send_buf[0];
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LOG_D("FLEXSPI Memory 32 bit Write End\n");
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2022-11-18 01:07:20 +08:00
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rt_memset(recv_buf, 0, sizeof(recv_buf));
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2022-11-18 01:05:04 +08:00
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2022-09-15 17:08:26 +08:00
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LOG_D("FLEXSPI Memory 32 bit Read Start\n");
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recv_buf[2] = *(flexspi + 11);
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recv_buf[3] = *(flexspi + 15);
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recv_buf[1] = *(flexspi + 8);
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recv_buf[0] = *(flexspi + 3);
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LOG_D("FLEXSPI Memory 32 bit Read End\n");
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LOG_D("addr12 is 0x%x\n", recv_buf[0]);
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LOG_D("addr32 is 0x%x\n", recv_buf[1]);
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LOG_D("addr44 is 0x%x\n", recv_buf[2]);
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LOG_D("addr60 is 0x%x\n", recv_buf[3]);
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}
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MSH_CMD_EXPORT(flexspi_test, flexspi test)
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#endif /* FLEXSPI_DEBUG */
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#endif /* FINSH_USING_MSH */
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#endif /* BSP_USING_FLEXSPI */
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