553 lines
26 KiB
C
553 lines
26 KiB
C
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/*
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* File : core_ck802.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2017-01-01 Urey first version
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*/
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#ifndef __CORE_CK802_H_GENERIC
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#define __CORE_CK802_H_GENERIC
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*******************************************************************************
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* CSI definitions
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******************************************************************************/
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/**
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\ingroup Ck802
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@{
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*/
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/* CSI CK802 definitions */
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#define __CK802_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
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#define __CK802_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
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#define __CK802_CSI_VERSION ((__CK802_CSI_VERSION_MAIN << 16U) | \
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__CK802_CSI_VERSION_SUB ) /*!< CSI HAL version number */
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#define __CK80X (0x02U) /*!< CK80X Core */
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/** __FPU_USED indicates whether an FPU is used or not.
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This core does not support an FPU at all
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*/
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#define __FPU_USED 0U
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#if defined ( __GNUC__ )
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#endif
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#include "csi_gcc.h"
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CORE_CK802_H_GENERIC */
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#ifndef __CSI_GENERIC
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#ifndef __CORE_CK802_H_DEPENDANT
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#define __CORE_CK802_H_DEPENDANT
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* check device defines and use defaults */
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//#if defined __CHECK_DEVICE_DEFINES
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#ifndef __CK802_REV
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#define __CK802_REV 0x0000U
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//#warning "__CK802_REV not defined in device header file; using default!"
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#endif
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#ifndef __NVIC_PRIO_BITS
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#define __NVIC_PRIO_BITS 2U
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//#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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#endif
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#ifndef __Vendor_SysTickConfig
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#define __Vendor_SysTickConfig 0U
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//#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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#endif
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#ifndef __GSR_GCR_PRESENT
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#define __GSR_GCR_PRESENT 0U
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//#warning "__GSR_GCR_PRESENT not defined in device header file; using default!"
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#endif
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#ifndef __MGU_PRESENT
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#define __MGU_PRESENT 0U
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//#warning "__MGU_PRESENT not defined in device header file; using default!"
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#endif
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//#endif
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/* IO definitions (access restrictions to peripheral registers) */
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/**
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\defgroup CSI_glob_defs CSI Global Defines
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<strong>IO Type Qualifiers</strong> are used
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\li to specify the access to peripheral variables.
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\li for automatic generation of peripheral register debug information.
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*/
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#ifdef __cplusplus
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#define __I volatile /*!< Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< Defines 'write only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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/* following defines should be used for structure members */
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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/*@} end of group CK802 */
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/*******************************************************************************
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* Register Abstraction
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Core Register contain:
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- Core Register
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- Core NVIC Register
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- Core SCB Register
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- Core SysTick Register
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******************************************************************************/
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/**
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\defgroup CSI_core_register Defines and Type Definitions
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\brief Type definitions and defines for CK80X processor based devices.
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*/
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/**
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\ingroup CSI_core_register
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\defgroup CSI_CORE Status and Control Registers
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\brief Core Register type definitions.
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@{
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*/
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/**
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\brief <EFBFBD><EFBFBD><EFBFBD>ʴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬<EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD>(PSR)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>嶨<EFBFBD><EFBFBD>.
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*/
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typedef union
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{
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struct
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{
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uint32_t C: 1; /*!< bit: 0 <20><><EFBFBD><EFBFBD><EFBFBD>룯<EFBFBD><EBA3AF>λλ */
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uint32_t _reserved0: 5; /*!< bit: 2.. 5 <20><><EFBFBD><EFBFBD> */
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uint32_t IE: 1; /*!< bit: 6 <20>ж<EFBFBD><D0B6><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD>λ */
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uint32_t IC: 1; /*!< bit: 7 <20>жϿ<D0B6><CFBF><EFBFBD>λ */
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uint32_t EE: 1; /*!< bit: 8 <20>쳣<EFBFBD><ECB3A3>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD>λ */
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uint32_t MM: 1; /*!< bit: 9 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>쳣<EFBFBD>ڸ<EFBFBD>λ */
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uint32_t _reserved1: 6; /*!< bit: 10..15 <20><><EFBFBD><EFBFBD> */
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uint32_t VEC: 8; /*!< bit: 16..23 <20>쳣<EFBFBD>¼<EFBFBD><C2BC><EFBFBD><EFBFBD><EFBFBD>ֵ */
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uint32_t _reserved2: 7; /*!< bit: 24..30 <20><><EFBFBD><EFBFBD> */
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uint32_t S: 1; /*!< bit: 31 <20><><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>λ */
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} b; /*!< Structure <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD> */
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uint32_t w; /*!< Type <20><><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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} PSR_Type;
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/* PSR Register Definitions */
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#define PSR_S_Pos 31U /*!< PSR: S Position */
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#define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
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#define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
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#define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
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#define PSR_MM_Pos 9U /*!< PSR: MM Position */
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#define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
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#define PSR_EE_Pos 8U /*!< PSR: EE Position */
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#define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
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#define PSR_IC_Pos 7U /*!< PSR: IC Position */
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#define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
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#define PSR_IE_Pos 6U /*!< PSR: IE Position */
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#define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
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#define PSR_C_Pos 0U /*!< PSR: C Position */
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#define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
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/**
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\brief <EFBFBD><EFBFBD><EFBFBD>ʸ<EFBFBD><EFBFBD>ٻ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>üĴ<EFBFBD><EFBFBD><EFBFBD>(CCR, CR<18, 0>)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>嶨<EFBFBD><EFBFBD>.
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*/
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typedef union
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{
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struct
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{
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uint32_t MP: 1; /*!< bit: 0 <20>ڴ汣<DAB4><E6B1A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t _reserved0: 6; /*!< bit: 1.. 6 <20><><EFBFBD><EFBFBD> */
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uint32_t BE: 1; /*!< bit: 7 Endianģʽ */
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uint32_t SCK: 3; /*!< bit: 8..10 ϵͳ<CFB5>ʹ<EFBFBD><CDB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӱ<EFBFBD> */
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uint32_t _reserved1: 2; /*!< bit: 11..12 <20><><EFBFBD><EFBFBD> */
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uint32_t BE_V2: 1; /*!< bit: 13 V2<56>汾<EFBFBD><E6B1BE>С<EFBFBD><D0A1> */
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uint32_t _reserved2: 18; /*!< bit: 14..31 <20><><EFBFBD><EFBFBD> */
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} b; /*!< Structure <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD> */
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uint32_t w; /*!< Type <20><><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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} CCR_Type;
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/* CCR Register Definitions */
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#define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
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#define CCR_BE_V2_Msk (0x1UL << CCR_ISR_Pos) /*!< CCR: BE_V2 Mask */
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#define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
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#define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
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#define CCR_BE_Pos 7U /*!< CCR: BE Position */
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#define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
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#define CCR_MP_Pos 0U /*!< CCR: MP Position */
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#define CCR_MP_Msk (0x1UL << CCR_MP_Pos) /*!< CCR: MP Mask */
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/**
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\brief <EFBFBD><EFBFBD><EFBFBD>ʿɸ<EFBFBD><EFBFBD>ͷ<EFBFBD><EFBFBD><EFBFBD>Ȩ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>üĴ<EFBFBD><EFBFBD><EFBFBD>(CAPR, CR<19,0>)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>嶨<EFBFBD><EFBFBD>..
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*/
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typedef union
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{
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struct
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{
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uint32_t X0: 1; /*!< bit: 0 <20><><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t X1: 1; /*!< bit: 1 <20><><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t X2: 1; /*!< bit: 2 <20><><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t X3: 1; /*!< bit: 3 <20><><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t X4: 1; /*!< bit: 4 <20><><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t X5: 1; /*!< bit: 5 <20><><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t X6: 1; /*!< bit: 6 <20><><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t X7: 1; /*!< bit: 7 <20><><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t AP0: 2; /*!< bit: 8.. 9 <20><><EFBFBD><EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t AP1: 2; /*!< bit: 10..11 <20><><EFBFBD><EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t AP2: 2; /*!< bit: 12..13 <20><><EFBFBD><EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t AP3: 2; /*!< bit: 14..15 <20><><EFBFBD><EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t AP4: 2; /*!< bit: 16..17 <20><><EFBFBD><EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t AP5: 2; /*!< bit: 18..19 <20><><EFBFBD><EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t AP6: 2; /*!< bit: 20..21 <20><><EFBFBD><EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t AP7: 2; /*!< bit: 22..23 <20><><EFBFBD><EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t S0: 1; /*!< bit: 24 <20><>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t S1: 1; /*!< bit: 25 <20><>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t S2: 1; /*!< bit: 26 <20><>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t S3: 1; /*!< bit: 27 <20><>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t S4: 1; /*!< bit: 28 <20><>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t S5: 1; /*!< bit: 29 <20><>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t S6: 1; /*!< bit: 30 <20><>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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uint32_t S7: 1; /*!< bit: 31 <20><>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
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} b; /*!< Structure <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD> */
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uint32_t w; /*!< Type <20><><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
|||
|
|
} CAPR_Type;
|
|||
|
|
|
|||
|
|
/* CAPR Register Definitions */
|
|||
|
|
#define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
|
|||
|
|
#define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
|
|||
|
|
#define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
|
|||
|
|
#define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
|
|||
|
|
#define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
|
|||
|
|
#define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
|
|||
|
|
#define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
|
|||
|
|
#define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
|
|||
|
|
#define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
|
|||
|
|
#define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
|
|||
|
|
#define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
|
|||
|
|
#define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
|
|||
|
|
#define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
|
|||
|
|
#define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
|
|||
|
|
#define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
|
|||
|
|
#define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
|
|||
|
|
#define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
|
|||
|
|
#define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
|
|||
|
|
#define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
|
|||
|
|
#define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
|
|||
|
|
#define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
|
|||
|
|
#define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
|
|||
|
|
#define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
|
|||
|
|
#define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
|
|||
|
|
|
|||
|
|
#define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
|
|||
|
|
#define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
\brief <EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƼĴ<EFBFBD><EFBFBD><EFBFBD>(PACR, CR<20,0>)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>嶨<EFBFBD><EFBFBD>.
|
|||
|
|
*/
|
|||
|
|
typedef union
|
|||
|
|
{
|
|||
|
|
struct
|
|||
|
|
{
|
|||
|
|
uint32_t E: 1; /*!< bit: 0 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD> */
|
|||
|
|
uint32_t Size: 5; /*!< bit: 1.. 5 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С */
|
|||
|
|
uint32_t _reserved0: 4; /*!< bit: 6.. 9 <20><><EFBFBD><EFBFBD> */
|
|||
|
|
uint32_t base_addr: 22; /*!< bit: 10..31 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD>ĸ<EFBFBD>λ */
|
|||
|
|
} b; /*!< Structure <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD> */
|
|||
|
|
uint32_t w; /*!< Type <20><><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
|||
|
|
} PACR_Type;
|
|||
|
|
|
|||
|
|
/* PACR Register Definitions */
|
|||
|
|
#define PACR_BASE_ADDR_Pos 10U /*!< PACR: base_addr Position */
|
|||
|
|
#define PACK_BASE_ADDR_Msk (0x3FFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
|
|||
|
|
|
|||
|
|
#define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
|
|||
|
|
#define PACK_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
|
|||
|
|
|
|||
|
|
#define PACR_E_Pos 0U /*!< PACR: E Position */
|
|||
|
|
#define PACK_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
\brief <EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD>(PRSR,CR<21,0>)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>嶨<EFBFBD><EFBFBD>.
|
|||
|
|
*/
|
|||
|
|
typedef union
|
|||
|
|
{
|
|||
|
|
struct
|
|||
|
|
{
|
|||
|
|
uint32_t RID: 3; /*!< bit: 0.. 2 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ */
|
|||
|
|
uint32_t _reserved0: 30; /*!< bit: 3..31 <20><><EFBFBD><EFBFBD> */
|
|||
|
|
} b; /*!< Structure <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD> */
|
|||
|
|
uint32_t w; /*!< Type <20><><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
|||
|
|
} PRSR_Type;
|
|||
|
|
|
|||
|
|
/* PRSR Register Definitions */
|
|||
|
|
#define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
|
|||
|
|
#define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
|
|||
|
|
|
|||
|
|
/*@} end of group CSI_CORE */
|
|||
|
|
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
\ingroup CSI_core_register
|
|||
|
|
\defgroup CSI_NVIC Vectored Interrupt Controller (NVIC)
|
|||
|
|
\brief Type definitions for the NVIC Registers
|
|||
|
|
@{
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
\brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʸ<EFBFBD><EFBFBD><EFBFBD>жϿ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ľṹ<EFBFBD><EFBFBD>.
|
|||
|
|
*/
|
|||
|
|
typedef struct
|
|||
|
|
{
|
|||
|
|
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) <20>ж<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD> */
|
|||
|
|
uint32_t RESERVED0[15U];
|
|||
|
|
__IOM uint32_t IWER[1U]; /*!< Offset: 0x040 (R/W) <20>жϵ<CFB5><CDB9>Ļ<EFBFBD><C4BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD> */
|
|||
|
|
uint32_t RESERVED1[15U];
|
|||
|
|
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) <20>ж<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD> */
|
|||
|
|
uint32_t RESERVED2[15U];
|
|||
|
|
__IOM uint32_t IWDR[1U]; /*!< Offset: 0x0c0 (R/W) <20>жϵ<CFB5><CDB9>Ļ<EFBFBD><C4BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD> */
|
|||
|
|
uint32_t RESERVED3[15U];
|
|||
|
|
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) <20>жϵȴ<CFB5><C8B4><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD> */
|
|||
|
|
uint32_t RESERVED4[15U];
|
|||
|
|
__IOM uint32_t ISSR[1U]; /*!< Offset: 0x140 (R/W) <20><>ȫ<EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD> */
|
|||
|
|
uint32_t RESERVED5[15U];
|
|||
|
|
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) <20>жϵȴ<CFB5><C8B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD> */
|
|||
|
|
uint32_t RESERVED6[31U];
|
|||
|
|
__IOM uint32_t IABR[1U]; /*!< Offset: 0x200 (R/W) <20>ж<EFBFBD><D0B6><EFBFBD>Ӧ״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD> */
|
|||
|
|
uint32_t RESERVED7[63U];
|
|||
|
|
__IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) <20>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>ȼ<EFBFBD><C8BC><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD> */
|
|||
|
|
uint32_t RESERVED8[504U];
|
|||
|
|
__IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) <20>ж<EFBFBD>״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD> */
|
|||
|
|
__IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) <20>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>ȼ<EFBFBD><C8BC><EFBFBD>ֵ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD> */
|
|||
|
|
} NVIC_Type;
|
|||
|
|
|
|||
|
|
/*@} end of group CSI_NVIC */
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
\ingroup CSI_core_register
|
|||
|
|
\defgroup CSI_SysTick System Tick Timer (CORET)
|
|||
|
|
\brief Type definitions for the System Timer Registers.
|
|||
|
|
@{
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
\brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵͳ<EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݽṹ.
|
|||
|
|
*/
|
|||
|
|
typedef struct
|
|||
|
|
{
|
|||
|
|
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) <20><><EFBFBD><EFBFBD>״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD> */
|
|||
|
|
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) <20><><EFBFBD><EFBFBD>ֵ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD> */
|
|||
|
|
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) <20><>ǰֵ<C7B0>Ĵ<EFBFBD><C4B4><EFBFBD> */
|
|||
|
|
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) У<D0A3>Ĵ<EFBFBD><C4B4><EFBFBD> */
|
|||
|
|
} CORET_Type;
|
|||
|
|
|
|||
|
|
/* CORET Control / Status Register Definitions */
|
|||
|
|
#define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
|
|||
|
|
#define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
|
|||
|
|
|
|||
|
|
#define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
|
|||
|
|
#define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
|
|||
|
|
|
|||
|
|
#define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
|
|||
|
|
#define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
|
|||
|
|
|
|||
|
|
#define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
|
|||
|
|
#define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
|
|||
|
|
|
|||
|
|
/* CORET Reload Register Definitions */
|
|||
|
|
#define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
|
|||
|
|
#define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
|
|||
|
|
|
|||
|
|
/* CORET Current Register Definitions */
|
|||
|
|
#define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
|
|||
|
|
#define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
|
|||
|
|
|
|||
|
|
/* CORET Calibration Register Definitions */
|
|||
|
|
#define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
|
|||
|
|
#define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
|
|||
|
|
|
|||
|
|
#define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
|
|||
|
|
#define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
|
|||
|
|
|
|||
|
|
#define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
|
|||
|
|
#define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
|
|||
|
|
|
|||
|
|
/*@} end of group CSI_SysTick */
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
\ingroup CSI_core_register
|
|||
|
|
\defgroup CSI_DCC
|
|||
|
|
\brief Type definitions for the DCC.
|
|||
|
|
@{
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
\brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>DCC<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݽṹ.
|
|||
|
|
*/
|
|||
|
|
typedef struct
|
|||
|
|
{
|
|||
|
|
uint32_t RESERVED0[13U];
|
|||
|
|
__IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
|
|||
|
|
__IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
|
|||
|
|
uint32_t RESERVED1[6U];
|
|||
|
|
union
|
|||
|
|
{
|
|||
|
|
__IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) <20><><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD> CPU<50><55>*/
|
|||
|
|
__OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) <20><><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD> CPUд*/
|
|||
|
|
};
|
|||
|
|
|
|||
|
|
} DCC_Type;
|
|||
|
|
|
|||
|
|
#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
|
|||
|
|
#define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
|
|||
|
|
|
|||
|
|
#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
|
|||
|
|
#define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
|
|||
|
|
|
|||
|
|
#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
|
|||
|
|
#define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
|
|||
|
|
|
|||
|
|
#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
|
|||
|
|
#define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
|
|||
|
|
|
|||
|
|
/*@} end of group CSI_DCC */
|
|||
|
|
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
\ingroup CSI_core_register
|
|||
|
|
\defgroup CSI_core_bitfield Core register bit field macros
|
|||
|
|
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
|||
|
|
@{
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
\brief Mask and shift a bit field value for use in a register bit range.
|
|||
|
|
\param[in] field Name of the register bit field.
|
|||
|
|
\param[in] value Value of the bit field.
|
|||
|
|
\return Masked and shifted value.
|
|||
|
|
*/
|
|||
|
|
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
\brief Mask and shift a register value to extract a bit filed value.
|
|||
|
|
\param[in] field Name of the register bit field.
|
|||
|
|
\param[in] value Value of register.
|
|||
|
|
\return Masked and shifted bit field value.
|
|||
|
|
*/
|
|||
|
|
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
|||
|
|
|
|||
|
|
/*@} end of group CSI_core_bitfield */
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
\ingroup CSI_core_register
|
|||
|
|
\defgroup CSI_core_base Core Definitions
|
|||
|
|
\brief Definitions for base addresses, unions, and structures.
|
|||
|
|
@{
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/* Memory mapping of CK802 Hardware */
|
|||
|
|
#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
|
|||
|
|
#define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
|
|||
|
|
#define NVIC_BASE (TCIP_BASE + 0x0100UL) /*!< NVIC Base Address */
|
|||
|
|
#define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
|
|||
|
|
|
|||
|
|
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
|
|||
|
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
|||
|
|
#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
|
|||
|
|
|
|||
|
|
/*@} */
|
|||
|
|
|
|||
|
|
#ifdef __cplusplus
|
|||
|
|
}
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
#endif /* __CORE_CK802_H_DEPENDANT */
|
|||
|
|
|
|||
|
|
#endif /* __CSI_GENERIC */
|