2022-06-29 00:00:58 +08:00
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-06-27 lianghongquan first version
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*/
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#include <board.h>
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#if (defined RT_USING_PWM) && (defined BSP_USING_PWM_TMRA)
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#include "drv_config.h"
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#include <drivers/rt_drv_pwm.h>
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//#define DRV_DEBUG
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#define LOG_TAG "drv.pwm.tmra"
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#include <drv_log.h>
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#if (!(defined(BSP_USING_PWM_TMRA_1) || defined(BSP_USING_PWM_TMRA_2) || \
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defined(BSP_USING_PWM_TMRA_3) || defined(BSP_USING_PWM_TMRA_4) || \
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defined(BSP_USING_PWM_TMRA_5) || defined(BSP_USING_PWM_TMRA_6)))
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#error "Please define at least one BSP_USING_PWM_TMRA_x"
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#endif
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enum
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{
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#ifdef BSP_USING_PWM_TMRA_1
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PWM_TMRA_1_INDEX,
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#endif
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#ifdef BSP_USING_PWM_TMRA_2
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PWM_TMRA_2_INDEX,
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#endif
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#ifdef BSP_USING_PWM_TMRA_3
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PWM_TMRA_3_INDEX,
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#endif
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#ifdef BSP_USING_PWM_TMRA_4
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PWM_TMRA_4_INDEX,
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#endif
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#ifdef BSP_USING_PWM_TMRA_5
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PWM_TMRA_5_INDEX,
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#endif
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#ifdef BSP_USING_PWM_TMRA_6
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PWM_TMRA_6_INDEX,
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#endif
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};
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struct hc32_pwm_tmra
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{
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struct rt_device_pwm pwm_device;
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CM_TMRA_TypeDef *instance;
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stc_tmra_init_t stcTmraInit;
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stc_tmra_pwm_init_t stcPwmInit;
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rt_uint8_t channel;
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char *name;
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};
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static struct hc32_pwm_tmra g_pwm_dev_array[] =
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{
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#ifdef BSP_USING_PWM_TMRA_1
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PWM_TMRA_1_CONFIG,
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#endif
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#ifdef BSP_USING_PWM_TMRA_2
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PWM_TMRA_2_CONFIG,
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#endif
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#ifdef BSP_USING_PWM_TMRA_3
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PWM_TMRA_3_CONFIG,
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#endif
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#ifdef BSP_USING_PWM_TMRA_4
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PWM_TMRA_4_CONFIG,
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#endif
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#ifdef BSP_USING_PWM_TMRA_5
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PWM_TMRA_5_CONFIG,
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#endif
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#ifdef BSP_USING_PWM_TMRA_6
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PWM_TMRA_6_CONFIG,
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#endif
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};
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static rt_uint32_t get_tmra_clk_freq_not_div(CM_TMRA_TypeDef *TMRAx)
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{
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stc_clock_freq_t stcClockFreq;
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CLK_GetClockFreq(&stcClockFreq);
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return stcClockFreq.u32Pclk1Freq;
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}
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static rt_uint32_t get_tmra_clk_freq(CM_TMRA_TypeDef *TMRAx)
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{
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rt_uint32_t u32clkFreq;
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uint16_t u16Div;
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//
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u32clkFreq = get_tmra_clk_freq_not_div(TMRAx);
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u16Div = READ_REG16(TMRAx->BCSTR) & TMRA_BCSTR_CKDIV;
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switch (u16Div)
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{
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case (TMRA_CLK_DIV2):
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u32clkFreq /= 2;
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break;
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case (TMRA_CLK_DIV4):
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u32clkFreq /= 4;
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break;
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case (TMRA_CLK_DIV8):
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u32clkFreq /= 8;
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break;
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case (TMRA_CLK_DIV16):
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u32clkFreq /= 16;
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break;
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case (TMRA_CLK_DIV32):
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u32clkFreq /= 32;
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break;
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case (TMRA_CLK_DIV64):
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u32clkFreq /= 64;
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break;
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case (TMRA_CLK_DIV128):
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u32clkFreq /= 128;
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break;
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case (TMRA_CLK_DIV256):
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u32clkFreq /= 256;
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break;
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case (TMRA_CLK_DIV512):
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u32clkFreq /= 512;
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break;
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case (TMRA_CLK_DIV1024):
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u32clkFreq /= 1024;
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break;
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case (TMRA_CLK_DIV1):
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default:
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break;
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}
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return u32clkFreq;
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}
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static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
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static struct rt_pwm_ops drv_ops =
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{
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drv_pwm_control
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};
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static rt_err_t drv_pwm_enable(CM_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration, rt_bool_t enable)
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{
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if (RT_TRUE == enable) {TMRA_PWM_OutputCmd(TMRAx, configuration->channel, ENABLE);}
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else {TMRA_PWM_OutputCmd(TMRAx, configuration->channel, DISABLE);}
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return RT_EOK;
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}
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static rt_err_t drv_pwm_get(CM_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration)
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{
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rt_uint32_t u32clkFreq;
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rt_uint64_t u64clk_ns;
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u32clkFreq = get_tmra_clk_freq(TMRAx);
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u64clk_ns = (rt_uint64_t)1000000000ul / u32clkFreq;
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configuration->period = u64clk_ns * TMRA_GetPeriodValue(TMRAx);
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configuration->pulse = u64clk_ns * TMRA_GetCompareValue(TMRAx, configuration->channel);
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return RT_EOK;
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}
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static rt_err_t drv_pwm_set(CM_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration)
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{
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rt_uint32_t u32clkFreq;
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rt_uint64_t u64clk_ns;
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rt_uint64_t u64val;
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//
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u32clkFreq = get_tmra_clk_freq(TMRAx);
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u64clk_ns = (rt_uint64_t)1000000000ul / u32clkFreq;
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u64val = (rt_uint64_t)configuration->period / u64clk_ns;
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if ((configuration->period <= u64clk_ns) || (u64val > 0xFFFF))
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{
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// clk not match, need change div
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uint32_t div_bit;
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u32clkFreq = get_tmra_clk_freq_not_div(TMRAx);
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u64clk_ns = (rt_uint64_t)1000000000ul / u32clkFreq;
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u64val = (rt_uint64_t)configuration->period / u64clk_ns;
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for (div_bit=0; div_bit<= 10; div_bit++)
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{
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if (u64val < 0xFFFF) break;
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u64val /= 2;
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}
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2023-03-17 12:12:16 +08:00
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if (div_bit > 10) return -RT_ERROR;
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2022-06-29 00:00:58 +08:00
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//
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TMRA_SetClockDiv(TMRAx, div_bit << TMRA_BCSTR_CKDIV_POS);
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u32clkFreq = get_tmra_clk_freq(TMRAx);
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u64clk_ns = (rt_uint64_t)1000000000ul / u32clkFreq;
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}
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TMRA_SetPeriodValue(TMRAx, configuration->period / u64clk_ns);
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TMRA_SetCompareValue(TMRAx, configuration->channel, configuration->pulse / u64clk_ns);
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return RT_EOK;
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}
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static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
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struct hc32_pwm_tmra *pwm;
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pwm = rt_container_of(device, struct hc32_pwm_tmra, pwm_device);
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CM_TMRA_TypeDef *TMRAx = pwm->instance;
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switch (cmd)
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{
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case PWMN_CMD_ENABLE:
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configuration->complementary = RT_TRUE;
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case PWM_CMD_ENABLE:
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return drv_pwm_enable(TMRAx, configuration, RT_TRUE);
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case PWMN_CMD_DISABLE:
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configuration->complementary = RT_FALSE;
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case PWM_CMD_DISABLE:
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return drv_pwm_enable(TMRAx, configuration, RT_FALSE);
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case PWM_CMD_SET:
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return drv_pwm_set(TMRAx, configuration);
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case PWM_CMD_GET:
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return drv_pwm_get(TMRAx, configuration);
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default:
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2023-03-16 12:44:05 +08:00
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return -RT_EINVAL;
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2022-06-29 00:00:58 +08:00
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}
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}
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static rt_err_t _pwm_tmra_init(struct hc32_pwm_tmra *device)
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{
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CM_TMRA_TypeDef *TMRAx;
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uint32_t i;
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//
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RT_ASSERT(device != RT_NULL);
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TMRAx = device->instance;
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TMRA_Init(TMRAx, &device->stcTmraInit);
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for (i=0; i<8; i++)
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{
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if ((device->channel >> i) & 0x01)
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{
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TMRA_PWM_Init(TMRAx, i, &device->stcPwmInit);
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}
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}
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TMRA_Start(TMRAx);
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return RT_EOK;
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}
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static void pwm_get_channel(void)
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{
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#ifdef BSP_USING_PWM_TMRA_1
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#ifdef BSP_USING_PWM_TMRA_1_CH1
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g_pwm_dev_array[PWM_TMRA_1_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM_TMRA_1_CH2
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g_pwm_dev_array[PWM_TMRA_1_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM_TMRA_1_CH3
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g_pwm_dev_array[PWM_TMRA_1_INDEX].channel |= 1 << 2;
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#endif
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#ifdef BSP_USING_PWM_TMRA_1_CH4
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g_pwm_dev_array[PWM_TMRA_1_INDEX].channel |= 1 << 3;
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#endif
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#ifdef BSP_USING_PWM_TMRA_1_CH5
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g_pwm_dev_array[PWM_TMRA_1_INDEX].channel |= 1 << 4;
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#endif
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#ifdef BSP_USING_PWM_TMRA_1_CH6
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g_pwm_dev_array[PWM_TMRA_1_INDEX].channel |= 1 << 5;
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#endif
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#ifdef BSP_USING_PWM_TMRA_1_CH7
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g_pwm_dev_array[PWM_TMRA_1_INDEX].channel |= 1 << 6;
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#endif
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#ifdef BSP_USING_PWM_TMRA_1_CH8
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g_pwm_dev_array[PWM_TMRA_1_INDEX].channel |= 1 << 7;
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#endif
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#endif
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#ifdef BSP_USING_PWM_TMRA_2
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#ifdef BSP_USING_PWM_TMRA_2_CH1
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g_pwm_dev_array[PWM_TMRA_2_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM_TMRA_2_CH2
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g_pwm_dev_array[PWM_TMRA_2_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM_TMRA_2_CH3
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g_pwm_dev_array[PWM_TMRA_2_INDEX].channel |= 1 << 2;
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#endif
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#ifdef BSP_USING_PWM_TMRA_2_CH4
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g_pwm_dev_array[PWM_TMRA_2_INDEX].channel |= 1 << 3;
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#endif
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#ifdef BSP_USING_PWM_TMRA_2_CH5
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g_pwm_dev_array[PWM_TMRA_2_INDEX].channel |= 1 << 4;
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#endif
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#ifdef BSP_USING_PWM_TMRA_2_CH6
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g_pwm_dev_array[PWM_TMRA_2_INDEX].channel |= 1 << 5;
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#endif
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#ifdef BSP_USING_PWM_TMRA_2_CH7
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g_pwm_dev_array[PWM_TMRA_2_INDEX].channel |= 1 << 6;
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#endif
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#ifdef BSP_USING_PWM_TMRA_2_CH8
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g_pwm_dev_array[PWM_TMRA_2_INDEX].channel |= 1 << 7;
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#endif
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#endif
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#ifdef BSP_USING_PWM_TMRA_3
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#ifdef BSP_USING_PWM_TMRA_3_CH1
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g_pwm_dev_array[PWM_TMRA_3_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM_TMRA_3_CH2
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g_pwm_dev_array[PWM_TMRA_3_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM_TMRA_3_CH3
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g_pwm_dev_array[PWM_TMRA_3_INDEX].channel |= 1 << 2;
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#endif
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#ifdef BSP_USING_PWM_TMRA_3_CH4
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g_pwm_dev_array[PWM_TMRA_3_INDEX].channel |= 1 << 3;
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#endif
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#ifdef BSP_USING_PWM_TMRA_3_CH5
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g_pwm_dev_array[PWM_TMRA_3_INDEX].channel |= 1 << 4;
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#endif
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#ifdef BSP_USING_PWM_TMRA_3_CH6
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g_pwm_dev_array[PWM_TMRA_3_INDEX].channel |= 1 << 5;
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#endif
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#ifdef BSP_USING_PWM_TMRA_3_CH7
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g_pwm_dev_array[PWM_TMRA_3_INDEX].channel |= 1 << 6;
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#endif
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#ifdef BSP_USING_PWM_TMRA_3_CH8
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g_pwm_dev_array[PWM_TMRA_3_INDEX].channel |= 1 << 7;
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#endif
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#endif
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#ifdef BSP_USING_PWM_TMRA_4
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#ifdef BSP_USING_PWM_TMRA_4_CH1
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g_pwm_dev_array[PWM_TMRA_4_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM_TMRA_4_CH2
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g_pwm_dev_array[PWM_TMRA_4_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM_TMRA_4_CH3
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g_pwm_dev_array[PWM_TMRA_4_INDEX].channel |= 1 << 2;
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#endif
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#ifdef BSP_USING_PWM_TMRA_4_CH4
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g_pwm_dev_array[PWM_TMRA_4_INDEX].channel |= 1 << 3;
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#endif
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#ifdef BSP_USING_PWM_TMRA_4_CH5
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g_pwm_dev_array[PWM_TMRA_4_INDEX].channel |= 1 << 4;
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#endif
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#ifdef BSP_USING_PWM_TMRA_4_CH6
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g_pwm_dev_array[PWM_TMRA_4_INDEX].channel |= 1 << 5;
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#endif
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#ifdef BSP_USING_PWM_TMRA_4_CH7
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g_pwm_dev_array[PWM_TMRA_4_INDEX].channel |= 1 << 6;
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#endif
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#ifdef BSP_USING_PWM_TMRA_4_CH8
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g_pwm_dev_array[PWM_TMRA_4_INDEX].channel |= 1 << 7;
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#endif
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#endif
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#ifdef BSP_USING_PWM_TMRA_5
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#ifdef BSP_USING_PWM_TMRA_5_CH1
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g_pwm_dev_array[PWM_TMRA_5_INDEX].channel |= 1 << 0;
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#endif
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#ifdef BSP_USING_PWM_TMRA_5_CH2
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g_pwm_dev_array[PWM_TMRA_5_INDEX].channel |= 1 << 1;
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#endif
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#ifdef BSP_USING_PWM_TMRA_5_CH3
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g_pwm_dev_array[PWM_TMRA_5_INDEX].channel |= 1 << 2;
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|
#endif
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#ifdef BSP_USING_PWM_TMRA_5_CH4
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g_pwm_dev_array[PWM_TMRA_5_INDEX].channel |= 1 << 3;
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|
#endif
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#ifdef BSP_USING_PWM_TMRA_5_CH5
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|
g_pwm_dev_array[PWM_TMRA_5_INDEX].channel |= 1 << 4;
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|
#endif
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|
#ifdef BSP_USING_PWM_TMRA_5_CH6
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|
g_pwm_dev_array[PWM_TMRA_5_INDEX].channel |= 1 << 5;
|
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|
#endif
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|
#ifdef BSP_USING_PWM_TMRA_5_CH7
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|
g_pwm_dev_array[PWM_TMRA_5_INDEX].channel |= 1 << 6;
|
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|
|
#endif
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|
#ifdef BSP_USING_PWM_TMRA_5_CH8
|
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|
|
g_pwm_dev_array[PWM_TMRA_5_INDEX].channel |= 1 << 7;
|
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|
|
#endif
|
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|
|
#endif
|
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|
#ifdef BSP_USING_PWM_TMRA_6
|
|
|
|
|
#ifdef BSP_USING_PWM_TMRA_6_CH1
|
|
|
|
|
g_pwm_dev_array[PWM_TMRA_6_INDEX].channel |= 1 << 0;
|
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|
|
|
#endif
|
|
|
|
|
#ifdef BSP_USING_PWM_TMRA_6_CH2
|
|
|
|
|
g_pwm_dev_array[PWM_TMRA_6_INDEX].channel |= 1 << 1;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef BSP_USING_PWM_TMRA_6_CH3
|
|
|
|
|
g_pwm_dev_array[PWM_TMRA_6_INDEX].channel |= 1 << 2;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef BSP_USING_PWM_TMRA_6_CH4
|
|
|
|
|
g_pwm_dev_array[PWM_TMRA_6_INDEX].channel |= 1 << 3;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef BSP_USING_PWM_TMRA_6_CH5
|
|
|
|
|
g_pwm_dev_array[PWM_TMRA_6_INDEX].channel |= 1 << 4;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef BSP_USING_PWM_TMRA_6_CH6
|
|
|
|
|
g_pwm_dev_array[PWM_TMRA_6_INDEX].channel |= 1 << 5;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef BSP_USING_PWM_TMRA_6_CH7
|
|
|
|
|
g_pwm_dev_array[PWM_TMRA_6_INDEX].channel |= 1 << 6;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef BSP_USING_PWM_TMRA_6_CH8
|
|
|
|
|
g_pwm_dev_array[PWM_TMRA_6_INDEX].channel |= 1 << 7;
|
|
|
|
|
#endif
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void _enable_periph_clk(void)
|
|
|
|
|
{
|
|
|
|
|
#ifdef BSP_USING_PWM_TMRA_1
|
|
|
|
|
FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMRA_1, ENABLE);
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef BSP_USING_PWM_TMRA_2
|
|
|
|
|
FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMRA_2, ENABLE);
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef BSP_USING_PWM_TMRA_3
|
|
|
|
|
FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMRA_3, ENABLE);
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef BSP_USING_PWM_TMRA_4
|
|
|
|
|
FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMRA_4, ENABLE);
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef BSP_USING_PWM_TMRA_5
|
|
|
|
|
FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMRA_5, ENABLE);
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef BSP_USING_PWM_TMRA_6
|
|
|
|
|
FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMRA_6, ENABLE);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
extern rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx);
|
|
|
|
|
static int rt_hw_pwm_tmra_init(void)
|
|
|
|
|
{
|
|
|
|
|
int i = 0;
|
|
|
|
|
rt_err_t result = RT_EOK;
|
|
|
|
|
|
|
|
|
|
pwm_get_channel();
|
|
|
|
|
_enable_periph_clk();
|
|
|
|
|
for (i = 0; i < sizeof(g_pwm_dev_array) / sizeof(g_pwm_dev_array[0]); i++)
|
|
|
|
|
{
|
|
|
|
|
/* pwm init */
|
|
|
|
|
_pwm_tmra_init(&g_pwm_dev_array[i]);
|
|
|
|
|
rt_hw_board_pwm_tmra_init(g_pwm_dev_array[i].instance);
|
|
|
|
|
/* register UART device */
|
|
|
|
|
result = rt_device_pwm_register(&g_pwm_dev_array[i].pwm_device, g_pwm_dev_array[i].name, &drv_ops, &g_pwm_dev_array[i].instance);
|
|
|
|
|
RT_ASSERT(result == RT_EOK);
|
|
|
|
|
}
|
|
|
|
|
return result;
|
|
|
|
|
}
|
|
|
|
|
INIT_DEVICE_EXPORT(rt_hw_pwm_tmra_init);
|
|
|
|
|
#endif /* RT_USING_PWM */
|
