321 lines
16 KiB
C
321 lines
16 KiB
C
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//*****************************************************************************
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//
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// hw_udma.h - Macros for use in accessing the UDMA registers.
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//
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// Copyright (c) 2007-2009 Luminary Micro, Inc. All rights reserved.
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws. All rights are reserved. You may not combine
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// this software with "viral" open-source software in order to form a larger
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// program. Any use in violation of the foregoing restrictions may subject
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// the user to criminal sanctions under applicable laws, as well as to civil
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// liability for the breach of the terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 4694 of the Stellaris Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_UDMA_H__
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#define __HW_UDMA_H__
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//*****************************************************************************
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//
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// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
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//
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//*****************************************************************************
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#define UDMA_STAT 0x400FF000 // DMA Status
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#define UDMA_CFG 0x400FF004 // DMA Configuration
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#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer
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#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control
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// Base Pointer
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#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait on Request
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// Status
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#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request
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#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set
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#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear
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#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set
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#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear
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#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set
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#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear
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#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate
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// Set
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#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate
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// Clear
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#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set
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#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear
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#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear
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#define UDMA_CHALT 0x400FF500 // DMA Channel Alternate Select
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#define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status
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//*****************************************************************************
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//
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// Micro Direct Memory Access (uDMA) offsets.
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//
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//*****************************************************************************
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#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
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// Pointer
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#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
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// End Pointer
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#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
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//
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//*****************************************************************************
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#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer.
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#define UDMA_SRCENDP_ADDR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_STAT register.
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//
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//*****************************************************************************
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#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available DMA Channels Minus 1.
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#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine State.
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#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle
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#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data
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#define UDMA_STAT_STATE_RD_SRCENDP \
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0x00000020 // Reading source end pointer
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#define UDMA_STAT_STATE_RD_DSTENDP \
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0x00000030 // Reading destination end pointer
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#define UDMA_STAT_STATE_RD_SRCDAT \
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0x00000040 // Reading source data
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#define UDMA_STAT_STATE_WR_DSTDAT \
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0x00000050 // Writing destination data
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#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for DMA request to clear
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#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data
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#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled
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#define UDMA_STAT_STATE_DONE 0x00000090 // Done
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#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined
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#define UDMA_STAT_MASTEN 0x00000001 // Master Enable.
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#define UDMA_STAT_DMACHANS_S 16
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
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//
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//*****************************************************************************
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#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer.
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#define UDMA_DSTENDP_ADDR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_CFG register.
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//
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//*****************************************************************************
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#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_CTLBASE register.
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//
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//*****************************************************************************
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#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address.
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#define UDMA_CTLBASE_ADDR_S 10
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_O_CHCTL register.
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//
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//*****************************************************************************
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#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment.
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#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
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#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
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#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
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#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
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#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size.
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#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
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#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
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#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
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#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment.
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#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
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#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
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#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
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#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
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#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size.
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#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
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#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
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#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
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#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size.
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#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
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#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
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#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
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#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
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#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
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#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
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#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
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#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
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#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
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#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
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#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
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#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1).
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#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst.
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#define UDMA_CHCTL_XFERMODE_M 0x00000007 // DMA Transfer Mode.
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#define UDMA_CHCTL_XFERMODE_STOP \
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0x00000000 // Stop
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#define UDMA_CHCTL_XFERMODE_BASIC \
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0x00000001 // Basic
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#define UDMA_CHCTL_XFERMODE_AUTO \
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0x00000002 // Auto-Request
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#define UDMA_CHCTL_XFERMODE_PINGPONG \
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0x00000003 // Ping-Pong
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#define UDMA_CHCTL_XFERMODE_MEM_SG \
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0x00000004 // Memory Scatter-Gather
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#define UDMA_CHCTL_XFERMODE_MEM_SGA \
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0x00000005 // Alternate Memory Scatter-Gather
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#define UDMA_CHCTL_XFERMODE_PER_SG \
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0x00000006 // Peripheral Scatter-Gather
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#define UDMA_CHCTL_XFERMODE_PER_SGA \
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0x00000007 // Alternate Peripheral
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// Scatter-Gather
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#define UDMA_CHCTL_XFERSIZE_S 4
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_ALTBASE register.
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//
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//*****************************************************************************
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#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
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// Pointer.
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#define UDMA_ALTBASE_ADDR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_WAITSTAT register.
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//
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//*****************************************************************************
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#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_SWREQ register.
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//
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//*****************************************************************************
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#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_USEBURSTSET
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// register.
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//
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//*****************************************************************************
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#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_USEBURSTCLR
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// register.
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//
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//*****************************************************************************
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#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_REQMASKSET
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// register.
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//
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//*****************************************************************************
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#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_REQMASKCLR
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// register.
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//
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//*****************************************************************************
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#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_ENASET register.
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//
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//*****************************************************************************
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#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_ENACLR register.
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//
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//*****************************************************************************
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#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_ALTSET register.
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//
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//*****************************************************************************
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#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_ALTCLR register.
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//
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//*****************************************************************************
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#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_PRIOSET register.
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//
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//*****************************************************************************
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#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_PRIOCLR register.
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//
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//*****************************************************************************
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#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_ERRCLR register.
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//
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//*****************************************************************************
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#define UDMA_ERRCLR_ERRCLR 0x00000001 // DMA Bus Error Status.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_CHALT register.
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//
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//*****************************************************************************
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#define UDMA_CHALT_M 0xFFFFFFFF // Channel [n] Alternate Assignment
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// Select.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_CHIS register.
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//
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//*****************************************************************************
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#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status.
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//*****************************************************************************
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//
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// The following definitions are deprecated.
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//
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//*****************************************************************************
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#ifndef DEPRECATED
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the UDMA_ENASET
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// register.
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//
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//*****************************************************************************
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#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set.
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#endif
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#endif // __HW_UDMA_H__
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