512 lines
13 KiB
C
512 lines
13 KiB
C
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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*2024-02-14 ShichengChu first version
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*/
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#include "drv_hw_i2c.h"
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#include <rtdevice.h>
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#include <board.h>
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#ifdef RT_USING_I2C
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#define DBG_TAG "drv.i2c"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#define false 0
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#define true 1
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struct _i2c_bus
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{
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struct rt_i2c_bus_device parent;
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uint8_t i2c_id;
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char *device_name;
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};
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static struct _i2c_bus _i2c_obj[] =
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{
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#ifdef BSP_USING_I2C0
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{
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.i2c_id = I2C0,
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.device_name = "i2c0",
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},
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#endif /* BSP_USING_I2C0 */
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#ifdef BSP_USING_I2C1
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{
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.i2c_id = I2C1,
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.device_name = "i2c1",
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},
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#endif /* BSP_USING_I2C1 */
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};
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static struct i2c_regs *get_i2c_base(uint8_t i2c_id)
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{
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struct i2c_regs *i2c_base = NULL;
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switch (i2c_id) {
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case I2C0:
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i2c_base = (struct i2c_regs *)I2C0_BASE;
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break;
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case I2C1:
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i2c_base = (struct i2c_regs *)I2C1_BASE;
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break;
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case I2C2:
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i2c_base = (struct i2c_regs *)I2C2_BASE;
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break;
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case I2C3:
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i2c_base = (struct i2c_regs *)I2C3_BASE;
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break;
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case I2C4:
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i2c_base = (struct i2c_regs *)I2C4_BASE;
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break;
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}
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return i2c_base;
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}
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static uint32_t get_i2c_intr(uint8_t i2c_id)
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{
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uint32_t i2c_intr = 0;
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switch (i2c_id) {
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case I2C0:
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i2c_intr = I2C0_IRQ;
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break;
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case I2C1:
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i2c_intr = I2C1_IRQ;
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break;
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case I2C2:
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i2c_intr = I2C2_IRQ;
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break;
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case I2C3:
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i2c_intr = I2C3_IRQ;
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break;
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case I2C4:
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i2c_intr = I2C4_IRQ;
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break;
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}
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return i2c_intr;
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}
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void i2c_write_cmd_data(struct i2c_regs *i2c, uint16_t value)
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{
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mmio_write_32((uintptr_t)&i2c->ic_cmd_data, value);
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}
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static void i2c_enable(struct i2c_regs *i2c, uint8_t enable)
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{
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uint32_t ena = enable ? IC_ENABLE : 0;
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int timeout = 100;
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do {
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mmio_write_32((uintptr_t)&i2c->ic_enable, ena);
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if ((mmio_read_32((uintptr_t)&i2c->ic_enable_status) & IC_ENABLE) == ena)
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return;
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/*
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* Wait 10 times the signaling period of the highest I2C
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* transfer supported by the driver (for 400KHz this is
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* 25us) as described in the DesignWare I2C databook.
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*/
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rt_hw_us_delay(25);
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} while (timeout--);
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LOG_I("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
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}
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static void i2c_disable(struct i2c_regs *i2c)
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{
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int timeout = 100;
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do {
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mmio_write_32((uintptr_t)&i2c->ic_enable, 0x0);
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if ((mmio_read_32((uintptr_t)&i2c->ic_enable_status) & IC_ENABLE) == 0x0)
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return;
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/*
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* Wait 10 times the signaling period of the highest I2C
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* transfer supported by the driver (for 400KHz this is
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* 25us) as described in the DesignWare I2C databook.
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*/
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rt_hw_us_delay(25);
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} while (timeout--);
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LOG_I("timeout in disabling I2C adapter\n");
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}
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/*
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* i2c_flush_rxfifo - Flushes the i2c RX FIFO
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*
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* Flushes the i2c RX FIFO
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*/
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static void i2c_flush_rxfifo(struct i2c_regs *i2c)
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{
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while (mmio_read_32((uintptr_t)&i2c->ic_status) & IC_STATUS_RFNE)
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mmio_read_32((uintptr_t)&i2c->ic_cmd_data);
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}
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/*
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* i2c_wait_for_bb - Waits for bus busy
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*
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* Waits for bus busy
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*/
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static int i2c_wait_for_bb(struct i2c_regs *i2c)
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{
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uint16_t timeout = 0;
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while ((mmio_read_32((uintptr_t)&i2c->ic_status) & IC_STATUS_MA) ||
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!(mmio_read_32((uintptr_t)&i2c->ic_status) & IC_STATUS_TFE)) {
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/* Evaluate timeout */
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rt_hw_us_delay(5);
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timeout++;
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if (timeout > 200) /* exceed 1 ms */
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return 1;
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}
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return 0;
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}
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/*
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* i2c_setaddress - Sets the target slave address
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* @i2c_addr: target i2c address
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*
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* Sets the target slave address.
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*/
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static void i2c_setaddress(struct i2c_regs *i2c, uint16_t i2c_addr)
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{
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/* Disable i2c */
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i2c_enable(i2c, false);
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mmio_write_32((uintptr_t)&i2c->ic_tar, i2c_addr);
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/* Enable i2c */
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i2c_enable(i2c, true);
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}
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static int i2c_xfer_init(struct i2c_regs *i2c, uint16_t chip, uint16_t addr, uint16_t alen)
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{
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if (i2c_wait_for_bb(i2c))
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return 1;
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i2c_setaddress(i2c, chip);
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while (alen) {
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alen--;
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/* high byte address going out first */
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i2c_write_cmd_data(i2c, (addr >> (alen * 8)) & 0xff); // TODO
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//mmio_write_32((uintptr_t)&i2c_base->ic_cmd_data, (addr >> (alen * 8)) & 0xff);
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}
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return 0;
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}
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static int i2c_xfer_finish(struct i2c_regs *i2c)
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{
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uint16_t timeout = 0;
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while (1) {
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if ((mmio_read_32((uintptr_t)&i2c->ic_raw_intr_stat) & IC_STOP_DET)) {
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mmio_read_32((uintptr_t)&i2c->ic_clr_stop_det);
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break;
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} else {
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timeout++;
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rt_hw_us_delay(5);
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if (timeout > I2C_STOPDET_TO * 100) {
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LOG_I("%s, tiemout\n", __func__);
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break;
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}
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}
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}
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if (i2c_wait_for_bb(i2c))
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return 1;
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i2c_flush_rxfifo(i2c);
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return 0;
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}
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/*
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* i2c_read - Read from i2c memory
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* @chip: target i2c address
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* @addr: address to read from
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* @alen:
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* @buffer: buffer for read data
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* @len: no of bytes to be read
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*
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* Read from i2c memory.
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*/
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static int hal_i2c_read(uint8_t i2c_id, uint8_t dev, uint16_t addr, uint16_t alen, uint8_t *buffer, uint16_t len)
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{
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unsigned int active = 0;
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unsigned int time_count = 0;
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struct i2c_regs *i2c;
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int ret = 0;
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i2c = get_i2c_base(i2c_id);
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i2c_enable(i2c, true);
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if (i2c_xfer_init(i2c, dev, addr, alen))
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return 1;
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while (len) {
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if (!active) {
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/*
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* Avoid writing to ic_cmd_data multiple times
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* in case this loop spins too quickly and the
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* ic_status RFNE bit isn't set after the first
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* write. Subsequent writes to ic_cmd_data can
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* trigger spurious i2c transfer.
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*/
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i2c_write_cmd_data(i2c, (dev <<1) | BIT_I2C_CMD_DATA_READ_BIT | BIT_I2C_CMD_DATA_STOP_BIT);
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//mmio_write_32((uintptr_t)&i2c_base->ic_cmd_data, (dev <<1) | BIT_I2C_CMD_DATA_READ_BIT | BIT_I2C_CMD_DATA_STOP_BIT);
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active = 1;
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}
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if (mmio_read_32((uintptr_t)&i2c->ic_raw_intr_stat) & BIT_I2C_INT_RX_FULL) {
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*buffer++ = (uint8_t)mmio_read_32((uintptr_t)&i2c->ic_cmd_data);
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len--;
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time_count = 0;
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active = 0;
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}
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else {
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rt_hw_us_delay(5);
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time_count++;
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if (time_count >= I2C_BYTE_TO * 100)
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return 1;
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}
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}
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ret = i2c_xfer_finish(i2c);
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i2c_disable(i2c);
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return ret;
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}
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/*
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* i2c_write - Write to i2c memory
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* @chip: target i2c address
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* @addr: address to read from
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* @alen:
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* @buffer: buffer for read data
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* @len: no of bytes to be read
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*
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* Write to i2c memory.
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*/
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static int hal_i2c_write(uint8_t i2c_id, uint8_t dev, uint16_t addr, uint16_t alen, uint8_t *buffer, uint16_t len)
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{
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struct i2c_regs *i2c;
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int ret = 0;
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i2c = get_i2c_base(i2c_id);
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i2c_enable(i2c, true);
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if (i2c_xfer_init(i2c, dev, addr, alen))
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return 1;
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while (len) {
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if (i2c->ic_status & IC_STATUS_TFNF) {
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if (--len == 0) {
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i2c_write_cmd_data(i2c, *buffer | IC_STOP);
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//mmio_write_32((uintptr_t)&i2c_base->ic_cmd_data, *buffer | IC_STOP);
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} else {
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i2c_write_cmd_data(i2c, *buffer);
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//mmio_write_32((uintptr_t)&i2c_base->ic_cmd_data, *buffer);
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}
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buffer++;
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} else
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LOG_I("len=%d, ic status is not TFNF\n", len);
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}
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ret = i2c_xfer_finish(i2c);
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i2c_disable(i2c);
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return ret;
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}
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/*
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* hal_i2c_set_bus_speed - Set the i2c speed
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* @speed: required i2c speed
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*
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* Set the i2c speed.
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*/
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static void i2c_set_bus_speed(struct i2c_regs *i2c, unsigned int speed)
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{
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unsigned int cntl;
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unsigned int hcnt, lcnt;
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int i2c_spd;
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if (speed > I2C_FAST_SPEED)
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i2c_spd = IC_SPEED_MODE_MAX;
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else if ((speed <= I2C_FAST_SPEED) && (speed > I2C_STANDARD_SPEED))
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i2c_spd = IC_SPEED_MODE_FAST;
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else
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i2c_spd = IC_SPEED_MODE_STANDARD;
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/* to set speed cltr must be disabled */
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i2c_enable(i2c, false);
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cntl = (mmio_read_32((uintptr_t)&i2c->ic_con) & (~IC_CON_SPD_MSK));
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switch (i2c_spd) {
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case IC_SPEED_MODE_MAX:
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cntl |= IC_CON_SPD_HS;
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//hcnt = (u16)(((IC_CLK * MIN_HS100pF_SCL_HIGHTIME) / 1000) - 8);
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/* 7 = 6+1 == MIN LEN +IC_FS_SPKLEN */
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//lcnt = (u16)(((IC_CLK * MIN_HS100pF_SCL_LOWTIME) / 1000) - 1);
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hcnt = 6;
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lcnt = 8;
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mmio_write_32((uintptr_t)&i2c->ic_hs_scl_hcnt, hcnt);
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mmio_write_32((uintptr_t)&i2c->ic_hs_scl_lcnt, lcnt);
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break;
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case IC_SPEED_MODE_STANDARD:
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|
|
cntl |= IC_CON_SPD_SS;
|
||
|
|
|
||
|
|
hcnt = (uint16_t)(((IC_CLK * MIN_SS_SCL_HIGHTIME) / 1000) - 7);
|
||
|
|
lcnt = (uint16_t)(((IC_CLK * MIN_SS_SCL_LOWTIME) / 1000) - 1);
|
||
|
|
|
||
|
|
mmio_write_32((uintptr_t)&i2c->ic_ss_scl_hcnt, hcnt);
|
||
|
|
mmio_write_32((uintptr_t)&i2c->ic_ss_scl_lcnt, lcnt);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case IC_SPEED_MODE_FAST:
|
||
|
|
default:
|
||
|
|
cntl |= IC_CON_SPD_FS;
|
||
|
|
hcnt = (uint16_t)(((IC_CLK * MIN_FS_SCL_HIGHTIME) / 1000) - 7);
|
||
|
|
lcnt = (uint16_t)(((IC_CLK * MIN_FS_SCL_LOWTIME) / 1000) - 1);
|
||
|
|
|
||
|
|
mmio_write_32((uintptr_t)&i2c->ic_fs_scl_hcnt, hcnt);
|
||
|
|
mmio_write_32((uintptr_t)&i2c->ic_fs_scl_lcnt, lcnt);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
mmio_write_32((uintptr_t)&i2c->ic_con, cntl);
|
||
|
|
|
||
|
|
/* Enable back i2c now speed set */
|
||
|
|
i2c_enable(i2c, true);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* __hal_i2c_init - Init function
|
||
|
|
* @speed: required i2c speed
|
||
|
|
* @slaveaddr: slave address for the device
|
||
|
|
*
|
||
|
|
* Initialization function.
|
||
|
|
*/
|
||
|
|
static void hal_i2c_init(uint8_t i2c_id)
|
||
|
|
{
|
||
|
|
struct i2c_regs *i2c;
|
||
|
|
uint32_t i2c_intr;
|
||
|
|
|
||
|
|
LOG_I("%s, i2c-%d\n", __func__, i2c_id);
|
||
|
|
/* Disable i2c */
|
||
|
|
//Need to acquire lock here
|
||
|
|
|
||
|
|
i2c = get_i2c_base(i2c_id);
|
||
|
|
i2c_intr = get_i2c_intr(i2c_id);
|
||
|
|
|
||
|
|
// request_irq(i2c_intr, i2c_dw_isr, 0, "IC2_INTR int", &dw_i2c[i2c_id]);
|
||
|
|
|
||
|
|
i2c_enable(i2c, false);
|
||
|
|
mmio_write_32((uintptr_t)&i2c->ic_con, (IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM | IC_CON_RE));
|
||
|
|
mmio_write_32((uintptr_t)&i2c->ic_rx_tl, IC_RX_TL);
|
||
|
|
mmio_write_32((uintptr_t)&i2c->ic_tx_tl, IC_TX_TL);
|
||
|
|
mmio_write_32((uintptr_t)&i2c->ic_intr_mask, 0x0);
|
||
|
|
i2c_set_bus_speed(i2c, I2C_SPEED);
|
||
|
|
//mmio_write_32((uintptr_t)&i2c->ic_sar, slaveaddr);
|
||
|
|
/* Enable i2c */
|
||
|
|
i2c_enable(i2c, false);
|
||
|
|
|
||
|
|
//Need to release lock here
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_ssize_t _master_xfer(struct rt_i2c_bus_device *bus,
|
||
|
|
struct rt_i2c_msg msgs[],
|
||
|
|
rt_uint32_t num)
|
||
|
|
{
|
||
|
|
struct rt_i2c_msg *msg;
|
||
|
|
rt_uint32_t i;
|
||
|
|
rt_ssize_t ret = -RT_ERROR;
|
||
|
|
|
||
|
|
struct _i2c_bus *i2c = (struct _i2c_bus *)bus;
|
||
|
|
|
||
|
|
for (i = 0; i < num; i++)
|
||
|
|
{
|
||
|
|
msg = &msgs[i];
|
||
|
|
|
||
|
|
if (msg->flags & RT_I2C_RD)
|
||
|
|
{
|
||
|
|
hal_i2c_read(i2c->i2c_id, msg->addr, RT_NULL, 1, msg->buf, msg->len);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
hal_i2c_write(i2c->i2c_id, msg->addr, RT_NULL, 1, msg->buf, msg->len);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void rt_hw_i2c_isr(int irqno, void *param)
|
||
|
|
{
|
||
|
|
uint32_t stat, enabled;
|
||
|
|
struct i2c_regs *i2c = (struct i2c_regs *)param;
|
||
|
|
|
||
|
|
enabled = mmio_read_32((uintptr_t)&i2c->ic_enable);
|
||
|
|
stat = mmio_read_32((uintptr_t)&i2c->ic_intr_stat);
|
||
|
|
|
||
|
|
LOG_I("i2c interrupt stat: 0x%08x", stat);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct rt_i2c_bus_device_ops i2c_ops =
|
||
|
|
{
|
||
|
|
.master_xfer = _master_xfer,
|
||
|
|
.slave_xfer = RT_NULL,
|
||
|
|
.i2c_bus_control = RT_NULL
|
||
|
|
};
|
||
|
|
|
||
|
|
int rt_hw_i2c_init(void)
|
||
|
|
{
|
||
|
|
int result = RT_EOK;
|
||
|
|
|
||
|
|
#ifdef BSP_USING_I2C0
|
||
|
|
PINMUX_CONFIG(IIC0_SCL, IIC0_SCL);
|
||
|
|
PINMUX_CONFIG(IIC0_SDA, IIC0_SDA);
|
||
|
|
#endif /* BSP_USING_I2C0 */
|
||
|
|
#ifdef BSP_USING_I2C1
|
||
|
|
PINMUX_CONFIG(PAD_MIPIRX1P, IIC1_SDA);
|
||
|
|
PINMUX_CONFIG(PAD_MIPIRX0N, IIC1_SCL);
|
||
|
|
#endif /* BSP_USING_I2C1 */
|
||
|
|
|
||
|
|
for (rt_size_t i = 0; i < sizeof(_i2c_obj) / sizeof(struct _i2c_bus); i++)
|
||
|
|
{
|
||
|
|
hal_i2c_init(_i2c_obj->i2c_id);
|
||
|
|
|
||
|
|
_i2c_obj[i].parent.ops = &i2c_ops;
|
||
|
|
|
||
|
|
/* register i2c device */
|
||
|
|
if (rt_i2c_bus_device_register(&_i2c_obj[i].parent, _i2c_obj[i].device_name) == RT_EOK)
|
||
|
|
{
|
||
|
|
LOG_D("%s init success", _i2c_obj[i].device_name);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
LOG_E("%s register failed", _i2c_obj[i].device_name);
|
||
|
|
result = -RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t irqno = get_i2c_intr(_i2c_obj[i].i2c_id);
|
||
|
|
struct i2c_regs *_i2c = get_i2c_base(_i2c_obj[i].i2c_id);
|
||
|
|
rt_hw_interrupt_install(irqno, rt_hw_i2c_isr, _i2c, _i2c_obj[i].device_name);
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
INIT_BOARD_EXPORT(rt_hw_i2c_init);
|
||
|
|
|
||
|
|
#endif /* RT_USING_I2C */
|