256 lines
11 KiB
C
256 lines
11 KiB
C
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/**************************************************************************//**
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* @file epwm.h
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* @version V1.00
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* $Revision: 3 $
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* $Date: 15/12/02 5:23p $
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* @brief NUC472/NUC442 EPWM driver header file
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*
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* @note
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* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __EPWM_H__
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#define __EPWM_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
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@{
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*/
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/** @addtogroup NUC472_442_EPWM_Driver EPWM Driver
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@{
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*/
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/** @addtogroup NUC472_442_EPWM_EXPORTED_CONSTANTS EPWM Exported Constants
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@{
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*/
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#define EPWM_CHANNEL_NUM (6) /*!< EPWM channel number \hideinitializer */
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#define EPWM_CH0 (0UL) /*!< EPWM channel 0 \hideinitializer */
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#define EPWM_CH1 (1UL) /*!< EPWM channel 1 \hideinitializer */
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#define EPWM_CH2 (2UL) /*!< EPWM channel 2 \hideinitializer */
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#define EPWM_CH3 (3UL) /*!< EPWM channel 3 \hideinitializer */
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#define EPWM_CH4 (4UL) /*!< EPWM channel 4 \hideinitializer */
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#define EPWM_CH5 (5UL) /*!< EPWM channel 5 \hideinitializer */
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#define EPWM_CH_0_MASK (1UL) /*!< EPWM channel 0 mask \hideinitializer */
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#define EPWM_CH_1_MASK (2UL) /*!< EPWM channel 1 mask \hideinitializer */
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#define EPWM_CH_2_MASK (4UL) /*!< EPWM channel 2 mask \hideinitializer */
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#define EPWM_CH_3_MASK (8UL) /*!< EPWM channel 3 mask \hideinitializer */
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#define EPWM_CH_4_MASK (16UL) /*!< EPWM channel 4 mask \hideinitializer */
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#define EPWM_CH_5_MASK (32UL) /*!< EPWM channel 5 mask \hideinitializer */
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#define EPWM_CH_6_MASK (64UL) /*!< EPWM channel 6 mask \hideinitializer */
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#define EPWM_CLK_DIV_1 (0UL) /*!< EPWM clock divide by 1 \hideinitializer */
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#define EPWM_CLK_DIV_2 (1UL) /*!< EPWM clock divide by 2 \hideinitializer */
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#define EPWM_CLK_DIV_4 (2UL) /*!< EPWM clock divide by 4 \hideinitializer */
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#define EPWM_CLK_DIV_16 (3UL) /*!< EPWM clock divide by 16 \hideinitializer */
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#define EPWM_EDGE_ALIGNED (0UL) /*!< EPWM working in edge aligned type \hideinitializer */
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#define EPWM_CENTER_ALIGNED (EPWM_CTL_CNTTYPE_Msk) /*!< EPWM working in center aligned type \hideinitializer */
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#define EPWM_BRK0_BKP0 (EPWM_CTL_BRKP0EN_Msk) /*!< Brake0 signal source from external pin BKP0 \hideinitializer */
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#define EPWM_BRK0_CPO0 (EPWM_CTL_CPO0BKEN_Msk) /*!< Brake0 signal source from analog comparator 0 output \hideinitializer */
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#define EPWM_BRK0_CPO1 (EPWM_CTL_CPO1BKEN_Msk) /*!< Brake0 signal source from analog comparator 1 output \hideinitializer */
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#define EPWM_BRK0_CPO2 (EPWM_CTL_CPO2BKEN_Msk) /*!< Brake0 signal source from analog comparator 2 output \hideinitializer */
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#define EPWM_BRK1_LVDBKEN (EPWM_CTL_LVDBKEN_Msk) /*!< Brake1 signal source from low level detection \hideinitializer */
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#define EPWM_BK1SEL_BKP1 (0UL << EPWM_CTL_BRK1SEL_Pos) /*!< Brake1 signal source from external pin BKP1 \hideinitializer */
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#define EPWM_BK1SEL_CPO0 (1UL << EPWM_CTL_BRK1SEL_Pos) /*!< Brake1 signal source from analog comparator 0 output \hideinitializer */
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#define EPWM_BK1SEL_CPO1 (2UL << EPWM_CTL_BRK1SEL_Pos) /*!< Brake1 signal source from analog comparator 1 output \hideinitializer */
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#define EPWM_BK1SEL_CPO2 (3UL << EPWM_CTL_BRK1SEL_Pos) /*!< Brake1 signal source from analog comparator 2 output \hideinitializer */
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#define EPWM_PERIOD_INT_UNDERFLOW (0) /*!< EPWM period interrupt trigger if counter underflow \hideinitializer */
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#define EPWM_PERIOD_INT_MATCH_CNR (EPWM_CTL_INTTYPE_Msk) /*!< EPWM period interrupt trigger if counter match CNR \hideinitializer */
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#define EPWM_MODE_INDEPENDENT (0UL) /*!< EPWM independent mode \hideinitializer */
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#define EPWM_MODE_COMPLEMENTARY (1UL) /*!< EPWM complementary mode \hideinitializer */
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#define EPWM_MODE_SYNCHRONIZED (2UL) /*!< EPWM synchronized mode \hideinitializer */
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/*@}*/ /* end of group NUC472_442_EPWM_EXPORTED_CONSTANTS */
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/** @addtogroup NUC472_442_EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions
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@{
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*/
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/**
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* @brief This macro enable complementary mode
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define EPWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = ((pwm)->CTL & ~EPWM_CTL_MODE_Msk) | (EPWM_MODE_COMPLEMENTARY << EPWM_CTL_MODE_Pos))
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/**
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* @brief This macro disable complementary mode, and enable independent mode.
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define EPWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL &= ~EPWM_CTL_MODE_Msk)
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/**
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* @brief This macro enable group mode
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define EPWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL |= EPWM_CTL_GROUPEN_Msk)
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/**
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* @brief This macro disable group mode
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define EPWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL &= ~EPWM_CTL_GROUPEN_Msk)
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/**
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* @brief This macro enable synchronous mode
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define EPWM_ENABLE_SYNC_MODE(pwm) ((pwm)->CTL = ((pwm)->CTL & ~EPWM_CTL_MODE_Msk) | (EPWM_MODE_SYNCHRONIZED << EPWM_CTL_MODE_Pos))
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/**
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* @brief This macro disable synchronous mode, and enable independent mode.
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* @param[in] pwm The base address of PWM module
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* @return None
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* \hideinitializer
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*/
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#define EPWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL = ((pwm)->CTL & ~EPWM_CTL_MODE_Msk))
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/**
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* @brief This macro enable output inverter of specified channel(s)
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
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* Bit 0 represents channel 0, bit 1 represents channel 1...
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* @return None
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* \hideinitializer
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*/
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#define EPWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) \
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do { \
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if ((u32ChannelMask)) \
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((pwm)->CTL |= EPWM_CTL_PINV_Msk); \
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else \
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((pwm)->CTL &= ~EPWM_CTL_PINV_Msk); \
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}while(0)
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/**
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* @brief This macro mask output output logic to high or low
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
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* Bit 0 represents channel 0, bit 1 represents channel 1...
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* @param[in] u32LevelMask Output logic to high or low
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* @return None
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* \hideinitializer
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*/
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#define EPWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) \
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do { \
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(pwm)->MSKEN = u32ChannelMask; \
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(pwm)->MSK = u32ChannelMask; \
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}while(0)
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/**
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* @brief This macro set the divider of the selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32Divider Clock divider of specified channel. Valid values are
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* - \ref EPWM_CLK_DIV_1
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* - \ref EPWM_CLK_DIV_2
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* - \ref EPWM_CLK_DIV_4
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* - \ref EPWM_CLK_DIV_16
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* @return None
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* \hideinitializer
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*/
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#define EPWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
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((pwm)->CTL = ((pwm)->CTL & ~EPWM_CTL_CLKDIV_Msk) | ((u32Divider) << EPWM_CTL_CLKDIV_Pos))
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/**
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* @brief This macro set the duty of the selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
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* @return None
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* @note This new setting will take effect on next PWM period
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* \hideinitializer
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*/
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#define EPWM_SET_CMR(pwm, u32ChannelNum, u32CMR) \
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do { \
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(pwm)->CMPDAT[(u32ChannelNum) >> 1] = (u32CMR); \
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(pwm)->CTL |= EPWM_CTL_LOAD_Msk; \
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}while(0)
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/**
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* @brief This macro set the period of the selected channel
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
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* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
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* @return None
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* @note This new setting will take effect on next PWM period
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* @note PWM counter will stop if period length set to 0
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* \hideinitializer
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*/
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#define EPWM_SET_CNR(pwm, u32ChannelNum, u32CNR) \
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do { \
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(pwm)->PERIOD = (u32CNR); \
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(pwm)->CTL |= EPWM_CTL_LOAD_Msk; \
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}while(0)
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/**
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* @brief This macro set the PWM aligned type
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask This parameter is not used
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* @param[in] u32AlignedType PWM aligned type, valid values are:
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* - \ref EPWM_EDGE_ALIGNED
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* - \ref EPWM_CENTER_ALIGNED
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* @return None
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* \hideinitializer
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*/
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#define EPWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
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((pwm)->CTL = ((pwm)->CTL & ~EPWM_CTL_CNTTYPE_Msk) | (u32AlignedType))
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uint32_t EPWM_ConfigOutputChannel(EPWM_T *pwm,
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uint32_t u32ChannelNum,
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uint32_t u32Frequency,
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uint32_t u32DutyCycle);
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void EPWM_Start (EPWM_T *pwm, uint32_t u32ChannelMask);
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void EPWM_Stop(EPWM_T *pwm, uint32_t u32ChannelMask);
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void EPWM_ForceStop(EPWM_T *pwm, uint32_t u32ChannelMask);
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void EPWM_EnableFaultBrake(EPWM_T *pwm,
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uint32_t u32ChannelMask,
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uint32_t u32LevelMask,
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uint32_t u32BrakeSource);
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void EPWM_ClearFaultBrakeFlag(EPWM_T *pwm, uint32_t u32BrakeSource);
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void EPWM_EnableOutput(EPWM_T *pwm, uint32_t u32ChannelMask);
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void EPWM_DisableOutput(EPWM_T *pwm, uint32_t u32ChannelMask);
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void EPWM_EnableDeadZone(EPWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
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void EPWM_DisableDeadZone(EPWM_T *pwm, uint32_t u32ChannelNum);
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void EPWM_EnableDutyInt(EPWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
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void EPWM_DisableDutyInt(EPWM_T *pwm, uint32_t u32ChannelNum);
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void EPWM_ClearDutyIntFlag(EPWM_T *pwm, uint32_t u32ChannelNum);
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uint32_t EPWM_GetDutyIntFlag(EPWM_T *pwm, uint32_t u32ChannelNum);
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void EPWM_EnableFaultBrakeInt(EPWM_T *pwm, uint32_t u32BrakeSource);
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void EPWM_DisableFaultBrakeInt(EPWM_T *pwm, uint32_t u32BrakeSource);
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void EPWM_ClearFaultBrakeIntFlag(EPWM_T *pwm, uint32_t u32BrakeSource);
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uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *pwm, uint32_t u32BrakeSource);
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void EPWM_EnablePeriodInt(EPWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
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void EPWM_DisablePeriodInt(EPWM_T *pwm, uint32_t u32ChannelNum);
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void EPWM_ClearPeriodIntFlag(EPWM_T *pwm, uint32_t u32ChannelNum);
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uint32_t EPWM_GetPeriodIntFlag(EPWM_T *pwm, uint32_t u32ChannelNum);
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/*@}*/ /* end of group NUC472_442_EPWM_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group NUC472_442_EPWM_Driver */
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/*@}*/ /* end of group NUC472_442_Device_Driver */
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#ifdef __cplusplus
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}
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#endif
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#endif //__EPWM_H__
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/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
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