338 lines
18 KiB
C
338 lines
18 KiB
C
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/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
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* File Name : stm32f10x_fsmc.h
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* Author : MCD Application Team
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* Version : V2.0.3Patch1
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* Date : 04/06/2009
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* Description : This file contains all the functions prototypes for the
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* FSMC firmware library.
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********************************************************************************
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F10x_FSMC_H
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#define __STM32F10x_FSMC_H
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x_map.h"
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/* Exported types ------------------------------------------------------------*/
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/* Timing parameters For NOR/SRAM Banks */
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typedef struct
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{
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u32 FSMC_AddressSetupTime;
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u32 FSMC_AddressHoldTime;
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u32 FSMC_DataSetupTime;
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u32 FSMC_BusTurnAroundDuration;
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u32 FSMC_CLKDivision;
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u32 FSMC_DataLatency;
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u32 FSMC_AccessMode;
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}FSMC_NORSRAMTimingInitTypeDef;
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/* FSMC NOR/SRAM Init structure definition */
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typedef struct
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{
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u32 FSMC_Bank;
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u32 FSMC_DataAddressMux;
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u32 FSMC_MemoryType;
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u32 FSMC_MemoryDataWidth;
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u32 FSMC_BurstAccessMode;
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u32 FSMC_WaitSignalPolarity;
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u32 FSMC_WrapMode;
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u32 FSMC_WaitSignalActive;
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u32 FSMC_WriteOperation;
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u32 FSMC_WaitSignal;
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u32 FSMC_ExtendedMode;
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u32 FSMC_WriteBurst;
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/* Timing Parameters for write and read access if the ExtendedMode is not used*/
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FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;
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/* Timing Parameters for write access if the ExtendedMode is used*/
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FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;
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}FSMC_NORSRAMInitTypeDef;
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/* Timing parameters For FSMC NAND and PCCARD Banks */
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typedef struct
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{
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u32 FSMC_SetupTime;
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u32 FSMC_WaitSetupTime;
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u32 FSMC_HoldSetupTime;
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u32 FSMC_HiZSetupTime;
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}FSMC_NAND_PCCARDTimingInitTypeDef;
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/* FSMC NAND Init structure definition */
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typedef struct
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{
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u32 FSMC_Bank;
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u32 FSMC_Waitfeature;
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u32 FSMC_MemoryDataWidth;
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u32 FSMC_ECC;
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u32 FSMC_ECCPageSize;
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u32 FSMC_TCLRSetupTime;
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u32 FSMC_TARSetupTime;
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/* FSMC Common Space Timing */
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FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;
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/* FSMC Attribute Space Timing */
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FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;
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}FSMC_NANDInitTypeDef;
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/* FSMC PCCARD Init structure definition */
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typedef struct
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{
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u32 FSMC_Waitfeature;
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u32 FSMC_TCLRSetupTime;
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u32 FSMC_TARSetupTime;
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/* FSMC Common Space Timing */
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FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;
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/* FSMC Attribute Space Timing */
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FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;
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/* FSMC IO Space Timing */
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FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct;
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}FSMC_PCCARDInitTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/*-------------------------------FSMC Banks definitions ----------------------*/
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#define FSMC_Bank1_NORSRAM1 ((u32)0x00000000)
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#define FSMC_Bank1_NORSRAM2 ((u32)0x00000002)
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#define FSMC_Bank1_NORSRAM3 ((u32)0x00000004)
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#define FSMC_Bank1_NORSRAM4 ((u32)0x00000006)
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#define FSMC_Bank2_NAND ((u32)0x00000010)
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#define FSMC_Bank3_NAND ((u32)0x00000100)
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#define FSMC_Bank4_PCCARD ((u32)0x00001000)
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#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
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((BANK) == FSMC_Bank1_NORSRAM2) || \
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((BANK) == FSMC_Bank1_NORSRAM3) || \
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((BANK) == FSMC_Bank1_NORSRAM4))
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#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
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((BANK) == FSMC_Bank3_NAND))
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#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
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((BANK) == FSMC_Bank3_NAND) || \
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((BANK) == FSMC_Bank4_PCCARD))
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#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
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((BANK) == FSMC_Bank3_NAND) || \
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((BANK) == FSMC_Bank4_PCCARD))
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/*------------------------------- NOR/SRAM Banks -----------------------------*/
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/* FSMC Data/Address Bus Multiplexing ----------------------------------------*/
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#define FSMC_DataAddressMux_Disable ((u32)0x00000000)
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#define FSMC_DataAddressMux_Enable ((u32)0x00000002)
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#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
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((MUX) == FSMC_DataAddressMux_Enable))
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/* FSMC Memory Type ----------------------------------------------------------*/
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#define FSMC_MemoryType_SRAM ((u32)0x00000000)
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#define FSMC_MemoryType_PSRAM ((u32)0x00000004)
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#define FSMC_MemoryType_NOR ((u32)0x00000008)
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#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
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((MEMORY) == FSMC_MemoryType_PSRAM)|| \
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((MEMORY) == FSMC_MemoryType_NOR))
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/* FSMC Data Width ----------------------------------------------------------*/
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#define FSMC_MemoryDataWidth_8b ((u32)0x00000000)
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#define FSMC_MemoryDataWidth_16b ((u32)0x00000010)
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#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
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((WIDTH) == FSMC_MemoryDataWidth_16b))
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/* FSMC Burst Access Mode ----------------------------------------------------*/
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#define FSMC_BurstAccessMode_Disable ((u32)0x00000000)
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#define FSMC_BurstAccessMode_Enable ((u32)0x00000100)
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#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
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((STATE) == FSMC_BurstAccessMode_Enable))
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/* FSMC Wait Signal Polarity -------------------------------------------------*/
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#define FSMC_WaitSignalPolarity_Low ((u32)0x00000000)
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#define FSMC_WaitSignalPolarity_High ((u32)0x00000200)
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#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
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((POLARITY) == FSMC_WaitSignalPolarity_High))
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/* FSMC Wrap Mode ------------------------------------------------------------*/
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#define FSMC_WrapMode_Disable ((u32)0x00000000)
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#define FSMC_WrapMode_Enable ((u32)0x00000400)
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#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
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((MODE) == FSMC_WrapMode_Enable))
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/* FSMC Wait Timing ----------------------------------------------------------*/
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#define FSMC_WaitSignalActive_BeforeWaitState ((u32)0x00000000)
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#define FSMC_WaitSignalActive_DuringWaitState ((u32)0x00000800)
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#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
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((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
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/* FSMC Write Operation ------------------------------------------------------*/
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#define FSMC_WriteOperation_Disable ((u32)0x00000000)
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#define FSMC_WriteOperation_Enable ((u32)0x00001000)
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#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
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((OPERATION) == FSMC_WriteOperation_Enable))
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/* FSMC Wait Signal ----------------------------------------------------------*/
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#define FSMC_WaitSignal_Disable ((u32)0x00000000)
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#define FSMC_WaitSignal_Enable ((u32)0x00002000)
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#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
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((SIGNAL) == FSMC_WaitSignal_Enable))
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/* FSMC Extended Mode --------------------------------------------------------*/
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#define FSMC_ExtendedMode_Disable ((u32)0x00000000)
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#define FSMC_ExtendedMode_Enable ((u32)0x00004000)
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#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
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((MODE) == FSMC_ExtendedMode_Enable))
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/* FSMC Write Burst ----------------------------------------------------------*/
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#define FSMC_WriteBurst_Disable ((u32)0x00000000)
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#define FSMC_WriteBurst_Enable ((u32)0x00080000)
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#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
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((BURST) == FSMC_WriteBurst_Enable))
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/* FSMC Address Setup Time ---------------------------------------------------*/
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#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
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/* FSMC Address Hold Time ----------------------------------------------------*/
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#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
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/* FSMC Data Setup Time ------------------------------------------------------*/
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#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
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/* FSMC Bus Turn around Duration ---------------------------------------------*/
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#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
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/* FSMC CLK Division ---------------------------------------------------------*/
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#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
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/* FSMC Data Latency ---------------------------------------------------------*/
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#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
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/* FSMC Access Mode ----------------------------------------------------------*/
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#define FSMC_AccessMode_A ((u32)0x00000000)
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#define FSMC_AccessMode_B ((u32)0x10000000)
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#define FSMC_AccessMode_C ((u32)0x20000000)
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#define FSMC_AccessMode_D ((u32)0x30000000)
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#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
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((MODE) == FSMC_AccessMode_B) || \
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((MODE) == FSMC_AccessMode_C) || \
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((MODE) == FSMC_AccessMode_D))
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/*----------------------------- NAND and PCCARD Banks ------------------------*/
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/* FSMC Wait feature ---------------------------------------------------------*/
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#define FSMC_Waitfeature_Disable ((u32)0x00000000)
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#define FSMC_Waitfeature_Enable ((u32)0x00000002)
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#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
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((FEATURE) == FSMC_Waitfeature_Enable))
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/* FSMC Memory Data Width ----------------------------------------------------*/
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#define FSMC_MemoryDataWidth_8b ((u32)0x00000000)
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#define FSMC_MemoryDataWidth_16b ((u32)0x00000010)
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#define IS_FSMC_DATA_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
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((WIDTH) == FSMC_MemoryDataWidth_16b))
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/* FSMC ECC ------------------------------------------------------------------*/
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#define FSMC_ECC_Disable ((u32)0x00000000)
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#define FSMC_ECC_Enable ((u32)0x00000040)
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#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
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((STATE) == FSMC_ECC_Enable))
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/* FSMC ECC Page Size --------------------------------------------------------*/
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#define FSMC_ECCPageSize_256Bytes ((u32)0x00000000)
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#define FSMC_ECCPageSize_512Bytes ((u32)0x00020000)
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#define FSMC_ECCPageSize_1024Bytes ((u32)0x00040000)
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#define FSMC_ECCPageSize_2048Bytes ((u32)0x00060000)
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#define FSMC_ECCPageSize_4096Bytes ((u32)0x00080000)
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#define FSMC_ECCPageSize_8192Bytes ((u32)0x000A0000)
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#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
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((SIZE) == FSMC_ECCPageSize_512Bytes) || \
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((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
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((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
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((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
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((SIZE) == FSMC_ECCPageSize_8192Bytes))
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/* FSMC TCLR Setup Time ------------------------------------------------------*/
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#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
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/* FSMC TAR Setup Time -------------------------------------------------------*/
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#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
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/* FSMC Setup Time ----------------------------------------------------*/
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#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
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/* FSMC Wait Setup Time -----------------------------------------------*/
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#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
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/* FSMC Hold Setup Time -----------------------------------------------*/
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#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
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/* FSMC HiZ Setup Time ------------------------------------------------*/
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#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
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/* FSMC Interrupt sources ----------------------------------------------------*/
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#define FSMC_IT_RisingEdge ((u32)0x00000008)
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#define FSMC_IT_Level ((u32)0x00000010)
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#define FSMC_IT_FallingEdge ((u32)0x00000020)
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#define IS_FSMC_IT(IT) ((((IT) & (u32)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
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#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
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((IT) == FSMC_IT_Level) || \
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((IT) == FSMC_IT_FallingEdge))
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/* FSMC Flags ----------------------------------------------------------------*/
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#define FSMC_FLAG_RisingEdge ((u32)0x00000001)
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#define FSMC_FLAG_Level ((u32)0x00000002)
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#define FSMC_FLAG_FallingEdge ((u32)0x00000004)
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#define FSMC_FLAG_FEMPT ((u32)0x00000040)
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#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
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((FLAG) == FSMC_FLAG_Level) || \
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((FLAG) == FSMC_FLAG_FallingEdge) || \
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((FLAG) == FSMC_FLAG_FEMPT))
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#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (u32)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions ------------------------------------------------------- */
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void FSMC_NORSRAMDeInit(u32 FSMC_Bank);
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void FSMC_NANDDeInit(u32 FSMC_Bank);
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void FSMC_PCCARDDeInit(void);
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void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
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void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
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void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
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void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
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void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
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void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
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void FSMC_NORSRAMCmd(u32 FSMC_Bank, FunctionalState NewState);
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void FSMC_NANDCmd(u32 FSMC_Bank, FunctionalState NewState);
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void FSMC_PCCARDCmd(FunctionalState NewState);
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void FSMC_NANDECCCmd(u32 FSMC_Bank, FunctionalState NewState);
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u32 FSMC_GetECC(u32 FSMC_Bank);
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void FSMC_ITConfig(u32 FSMC_Bank, u32 FSMC_IT, FunctionalState NewState);
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FlagStatus FSMC_GetFlagStatus(u32 FSMC_Bank, u32 FSMC_FLAG);
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void FSMC_ClearFlag(u32 FSMC_Bank, u32 FSMC_FLAG);
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ITStatus FSMC_GetITStatus(u32 FSMC_Bank, u32 FSMC_IT);
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void FSMC_ClearITPendingBit(u32 FSMC_Bank, u32 FSMC_IT);
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#endif /*__STM32F10x_FSMC_H */
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/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
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