769 lines
21 KiB
C
769 lines
21 KiB
C
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/*
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* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/******************************************************************************
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* @file dw_usart.c
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* @brief CSI Source File for usart Driver
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* @version V1.0
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* @date 02. June 2017
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******************************************************************************/
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#include <stdbool.h>
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#include "csi_core.h"
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#include "drv_usart.h"
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#include "dw_usart.h"
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#include "soc.h"
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#define ERR_USART(errno) (CSI_DRV_ERRNO_USART_BASE | errno)
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/*
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* setting config may be accessed when the USART is not
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* busy(USR[0]=0) and the DLAB bit(LCR[7]) is set.
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*/
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#define WAIT_USART_IDLE(addr)\
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do { \
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int32_t timecount = 0; \
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while ((addr->USR & USR_UART_BUSY) && (timecount < UART_BUSY_TIMEOUT)) {\
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timecount++;\
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}\
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if (timecount >= UART_BUSY_TIMEOUT) {\
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return ERR_USART(EDRV_TIMEOUT);\
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} \
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} while(0)
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#define USART_NULL_PARAM_CHK(para) \
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do { \
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if (para == NULL) { \
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return ERR_USART(EDRV_PARAMETER); \
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} \
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} while (0)
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typedef struct {
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uint32_t base;
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uint32_t irq;
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usart_event_cb_t cb_event; ///< Event callback
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void *cb_arg;
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uint32_t rx_total_num;
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uint32_t tx_total_num;
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uint8_t *rx_buf;
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uint8_t *tx_buf;
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volatile uint32_t rx_cnt;
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volatile uint32_t tx_cnt;
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volatile uint32_t tx_busy;
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volatile uint32_t rx_busy;
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} dw_usart_priv_t;
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static dw_usart_priv_t usart_instance[CONFIG_USART_NUM];
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static const usart_capabilities_t usart_capabilities = {
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.asynchronous = 1, /* supports USART (Asynchronous) mode */
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.synchronous_master = 0, /* supports Synchronous Master mode */
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.synchronous_slave = 0, /* supports Synchronous Slave mode */
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.single_wire = 0, /* supports USART Single-wire mode */
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.event_tx_complete = 1, /* Transmit completed event */
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.event_rx_timeout = 0, /* Signal receive character timeout event */
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};
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/**
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\brief set the bautrate of usart.
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\param[in] addr usart base to operate.
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\param[in] baudrate.
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\param[in] apbfreq the frequence of the apb.
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\return error code
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*/
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static int32_t dw_usart_set_baudrate(dw_usart_reg_t *addr, uint32_t baudrate, uint32_t apbfreq)
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{
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WAIT_USART_IDLE(addr);
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/* baudrate=(seriak clock freq)/(16*divisor); algorithm :rounding*/
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uint32_t divisor = ((apbfreq * 10) / baudrate) >> 4;
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if ((divisor % 10) >= 5) {
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divisor = (divisor / 10) + 1;
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} else {
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divisor = divisor / 10;
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}
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addr->LCR |= LCR_SET_DLAB;
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/* DLL and DLH is lower 8-bits and higher 8-bits of divisor.*/
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addr->DLL = divisor & 0xff;
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addr->DLH = (divisor >> 8) & 0xff;
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/*
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* The DLAB must be cleared after the baudrate is setted
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* to access other registers.
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*/
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addr->LCR &= (~LCR_SET_DLAB);
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return 0;
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}
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/**
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\brief enable or disable parity.
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\param[in] addr usart base to operate.
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\param[in] parity ODD=8, EVEN=16, or NONE=0.
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\return error code
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*/
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static int32_t dw_usart_set_parity(dw_usart_reg_t *addr, usart_parity_e parity)
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{
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WAIT_USART_IDLE(addr);
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switch (parity) {
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case USART_PARITY_NONE:
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/*CLear the PEN bit(LCR[3]) to disable parity.*/
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addr->LCR &= (~LCR_PARITY_ENABLE);
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break;
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case USART_PARITY_ODD:
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/* Set PEN and clear EPS(LCR[4]) to set the ODD parity. */
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addr->LCR |= LCR_PARITY_ENABLE;
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addr->LCR &= LCR_PARITY_ODD;
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break;
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case USART_PARITY_EVEN:
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/* Set PEN and EPS(LCR[4]) to set the EVEN parity.*/
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addr->LCR |= LCR_PARITY_ENABLE;
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addr->LCR |= LCR_PARITY_EVEN;
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break;
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default:
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return ERR_USART(EDRV_USART_PARITY);
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}
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return 0;
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}
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/**
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\brief set the stop bit.
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\param[in] addr usart base to operate.
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\param[in] stopbit two possible value: USART_STOP_BITS_1 and USART_STOP_BITS_2.
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\return error code
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*/
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static int32_t dw_usart_set_stopbit(dw_usart_reg_t *addr, usart_stop_bits_e stopbit)
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{
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WAIT_USART_IDLE(addr);
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switch (stopbit) {
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case USART_STOP_BITS_1:
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/* Clear the STOP bit to set 1 stop bit*/
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addr->LCR &= LCR_STOP_BIT1;
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break;
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case USART_STOP_BITS_2:
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/*
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* If the STOP bit is set "1",we'd gotten 1.5 stop
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* bits when DLS(LCR[1:0]) is zero, else 2 stop bits.
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*/
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addr->LCR |= LCR_STOP_BIT2;
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break;
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default:
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return ERR_USART(EDRV_USART_STOP_BITS);
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}
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return 0;
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}
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/**
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\brief the transmit data length,and we have four choices:5, 6, 7, and 8 bits.
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\param[in] addr usart base to operate.
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\param[in] databits the data length that user decides.
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\return error code
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*/
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static int32_t dw_usart_set_databit(dw_usart_reg_t *addr, usart_data_bits_e databits)
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{
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WAIT_USART_IDLE(addr);
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/* The word size decides by the DLS bits(LCR[1:0]), and the
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* corresponding relationship between them is:
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* DLS word size
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* 00 -- 5 bits
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* 01 -- 6 bits
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* 10 -- 7 bits
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* 11 -- 8 bits
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*/
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switch (databits) {
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case USART_DATA_BITS_5:
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addr->LCR &= LCR_WORD_SIZE_5;
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break;
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case USART_DATA_BITS_6:
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addr->LCR &= 0xfd;
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addr->LCR |= LCR_WORD_SIZE_6;
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break;
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case USART_DATA_BITS_7:
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addr->LCR &= 0xfe;
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addr->LCR |= LCR_WORD_SIZE_7;
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break;
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case USART_DATA_BITS_8:
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addr->LCR |= LCR_WORD_SIZE_8;
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break;
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default:
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return ERR_USART(EDRV_USART_DATA_BITS);
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}
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return 0;
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}
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/**
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\brief get character in query mode.
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\param[in] instance usart instance to operate.
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\param[in] the pointer to the recieve charater.
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\return error code
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*/
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int32_t dw_usart_getchar(usart_handle_t handle, uint8_t *ch)
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{
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dw_usart_priv_t *usart_priv = handle;
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dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base);
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while (!(addr->LSR & LSR_DATA_READY));
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*ch = addr->RBR;
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return 0;
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}
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/**
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\brief get character in query mode.
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\param[in] instance usart instance to operate.
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\param[in] the pointer to the recieve charater.
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\return error code
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*/
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int32_t dw_usart_getchar_no_poll(usart_handle_t handle, uint8_t *ch)
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{
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dw_usart_priv_t *usart_priv = handle;
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dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base);
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if (addr->LSR & LSR_DATA_READY)
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{
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*ch = addr->RBR;
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return 0;
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}
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else
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{
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return -1;
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}
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}
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int32_t dw_usart_set_int_flag(usart_handle_t handle,uint32_t flag)
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{
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dw_usart_priv_t *usart_priv = handle;
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dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base);
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addr->IER |= flag;
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return 0;
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}
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int32_t dw_usart_clr_int_flag(usart_handle_t handle,uint32_t flag)
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{
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dw_usart_priv_t *usart_priv = handle;
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dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base);
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addr->IER &= ~flag;
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return 0;
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}
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/**
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\brief transmit character in query mode.
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\param[in] instance usart instance to operate.
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\param[in] ch the input charater
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\return error code
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*/
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int32_t dw_usart_putchar(usart_handle_t handle, uint8_t ch)
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{
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dw_usart_priv_t *usart_priv = handle;
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dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base);
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while ((!(addr->LSR & DW_LSR_TRANS_EMPTY)));
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if (ch == '\n')
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{
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addr->THR = '\r';
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while ((!(addr->LSR & DW_LSR_TRANS_EMPTY))) ;
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}
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addr->THR = ch;
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return 0;
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}
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/**
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\brief interrupt service function for transmitter holding register empty.
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\param[in] usart_priv usart private to operate.
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*/
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static void dw_usart_intr_threshold_empty(dw_usart_priv_t *usart_priv)
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{
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if (usart_priv->tx_total_num == 0) {
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return;
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}
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uint8_t remain_txdata = usart_priv->tx_total_num - usart_priv->tx_cnt;
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uint8_t txdata_num = (remain_txdata > UART_MAX_FIFO) ? UART_MAX_FIFO : remain_txdata;
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dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base);
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uint8_t i = 0u;
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for (i = 0; i < txdata_num; i++) {
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addr->THR = *((uint8_t *)usart_priv->tx_buf);
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usart_priv->tx_cnt++;
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usart_priv->tx_buf++;
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}
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if (usart_priv->tx_cnt >= usart_priv->tx_total_num) {
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addr->IER &= (~IER_THRE_INT_ENABLE);
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while ((!(addr->LSR & DW_LSR_TEMT)));
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usart_priv->tx_cnt = 0;
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usart_priv->tx_busy = 0;
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usart_priv->tx_buf = NULL;
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usart_priv->tx_total_num = 0;
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if (usart_priv->cb_event) {
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usart_priv->cb_event(USART_EVENT_SEND_COMPLETE, usart_priv->cb_arg);
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}
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}
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}
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/**
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\brief interrupt service function for receiver data available.
|
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\param[in] usart_priv usart private to operate.
|
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*/
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static void dw_usart_intr_recv_data(dw_usart_priv_t *usart_priv)
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{
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if (usart_priv->cb_event && (usart_priv->rx_total_num == 0)) {
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usart_priv->cb_event(USART_EVENT_RECEIVED, usart_priv->cb_arg);
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return;
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}
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dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base);
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uint8_t data = addr->RBR;
|
||
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if ((usart_priv->rx_total_num == 0) || (usart_priv->rx_buf == NULL)) {
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return;
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||
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}
|
||
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||
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*((uint8_t *)usart_priv->rx_buf) = data;
|
||
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usart_priv->rx_cnt++;
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||
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usart_priv->rx_buf++;
|
||
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||
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if (usart_priv->rx_cnt >= usart_priv->rx_total_num) {
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||
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usart_priv->rx_cnt = 0;
|
||
|
|
usart_priv->rx_buf = NULL;
|
||
|
|
usart_priv->rx_busy = 0;
|
||
|
|
usart_priv->rx_total_num = 0;
|
||
|
|
|
||
|
|
if (usart_priv->cb_event) {
|
||
|
|
usart_priv->cb_event(USART_EVENT_RECEIVE_COMPLETE, usart_priv->cb_arg);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief the interrupt service function.
|
||
|
|
\param[in] index of usart instance.
|
||
|
|
*/
|
||
|
|
void dw_usart_irqhandler(int32_t idx)
|
||
|
|
{
|
||
|
|
dw_usart_priv_t *usart_priv = &usart_instance[idx];
|
||
|
|
dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base);
|
||
|
|
|
||
|
|
uint8_t intr_state = addr->IIR & 0xf;
|
||
|
|
|
||
|
|
switch (intr_state) {
|
||
|
|
case DW_IIR_THR_EMPTY: /* interrupt source:transmitter holding register empty */
|
||
|
|
dw_usart_intr_threshold_empty(usart_priv);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case DW_IIR_RECV_DATA: /* interrupt source:receiver data available or receiver fifo trigger level reached */
|
||
|
|
dw_usart_intr_recv_data(usart_priv);
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
int32_t __attribute__((weak)) target_usart_init(pin_t tx, pin_t rx, uint32_t *base, uint32_t *irq)
|
||
|
|
{
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Get driver capabilities.
|
||
|
|
\param[in] handle usart handle to operate.
|
||
|
|
\return \ref usart_capabilities_t
|
||
|
|
*/
|
||
|
|
usart_capabilities_t csi_usart_get_capabilities(usart_handle_t handle)
|
||
|
|
{
|
||
|
|
return usart_capabilities;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Initialize USART Interface. 1. Initializes the resources needed for the USART interface 2.registers event callback function
|
||
|
|
\param[in] usart pin of tx
|
||
|
|
\param[in] usart pin of rx
|
||
|
|
\param[in] cb_event Pointer to \ref usart_event_cb_t
|
||
|
|
\return return usart handle if success
|
||
|
|
*/
|
||
|
|
usart_handle_t csi_usart_initialize(pin_t tx, pin_t rx, usart_event_cb_t cb_event, void *cb_arg)
|
||
|
|
{
|
||
|
|
uint32_t base = 0u;
|
||
|
|
uint32_t irq = 0u;
|
||
|
|
|
||
|
|
int32_t idx = target_usart_init(tx, rx, &base, &irq);
|
||
|
|
|
||
|
|
if (idx < 0 || idx >= CONFIG_USART_NUM) {
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
dw_usart_priv_t *usart_priv = &usart_instance[idx];
|
||
|
|
usart_priv->base = base;
|
||
|
|
usart_priv->irq = irq;
|
||
|
|
usart_priv->cb_event = cb_event;
|
||
|
|
usart_priv->cb_arg = cb_arg;
|
||
|
|
|
||
|
|
dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base);
|
||
|
|
/* FIFO enable */
|
||
|
|
addr->FCR = DW_FCR_FIFOE;
|
||
|
|
// /* enable received data available */
|
||
|
|
// addr->IER = IER_RDA_INT_ENABLE;
|
||
|
|
drv_nvic_enable_irq(usart_priv->irq);
|
||
|
|
|
||
|
|
return usart_priv;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief De-initialize UART Interface. stops operation and releases the software resources used by the interface
|
||
|
|
\param[in] handle usart handle to operate.
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_usart_uninitialize(usart_handle_t handle)
|
||
|
|
{
|
||
|
|
USART_NULL_PARAM_CHK(handle);
|
||
|
|
|
||
|
|
dw_usart_priv_t *usart_priv = handle;
|
||
|
|
|
||
|
|
drv_nvic_disable_irq(usart_priv->irq);
|
||
|
|
usart_priv->cb_event = NULL;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief config usart mode.
|
||
|
|
\param[in] handle usart handle to operate.
|
||
|
|
\param[in] sysclk configured system clock.
|
||
|
|
\param[in] mode \ref usart_mode_e
|
||
|
|
\param[in] parity \ref usart_parity_e
|
||
|
|
\param[in] stopbits \ref usart_stop_bits_e
|
||
|
|
\param[in] bits \ref usart_data_bits_e
|
||
|
|
\param[in] baud configured baud
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_usart_config(usart_handle_t handle,
|
||
|
|
uint32_t sysclk,
|
||
|
|
uint32_t baud,
|
||
|
|
usart_mode_e mode,
|
||
|
|
usart_parity_e parity,
|
||
|
|
usart_stop_bits_e stopbits,
|
||
|
|
usart_data_bits_e bits)
|
||
|
|
{
|
||
|
|
USART_NULL_PARAM_CHK(handle);
|
||
|
|
dw_usart_priv_t *usart_priv = handle;
|
||
|
|
dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base);
|
||
|
|
|
||
|
|
/* control the data_bit of the usart*/
|
||
|
|
int32_t ret = dw_usart_set_baudrate(addr, baud, sysclk);
|
||
|
|
|
||
|
|
if (ret < 0) {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* control the parity of the usart*/
|
||
|
|
ret = dw_usart_set_parity(addr, parity);
|
||
|
|
|
||
|
|
if (ret < 0) {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* control the stopbit of the usart*/
|
||
|
|
ret = dw_usart_set_stopbit(addr, stopbits);
|
||
|
|
|
||
|
|
if (ret < 0) {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = dw_usart_set_databit(addr, bits);
|
||
|
|
|
||
|
|
if (ret < 0) {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
/**
|
||
|
|
\brief config usart default tx value. used in syn mode
|
||
|
|
\param[in] handle usart handle to operate.
|
||
|
|
\param[in] value default tx value
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_usart_set_default_tx_value(usart_handle_t handle, uint32_t value)
|
||
|
|
{
|
||
|
|
USART_NULL_PARAM_CHK(handle);
|
||
|
|
return ERR_USART(EDRV_UNSUPPORTED);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Start sending data to UART transmitter,(received data is ignored).
|
||
|
|
The function is non-blocking,UART_EVENT_TRANSFER_COMPLETE is signaled when transfer completes.
|
||
|
|
csi_usart_get_status can indicates if transmission is still in progress or pending
|
||
|
|
\param[in] handle usart handle to operate.
|
||
|
|
\param[in] data Pointer to buffer with data to send to UART transmitter. data_type is : uint8_t for 1..8 data bits, uint16_t for 9..16 data bits,uint32_t for 17..32 data bits,
|
||
|
|
\param[in] num Number of data items to send
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_usart_send(usart_handle_t handle, const void *data, uint32_t num)
|
||
|
|
{
|
||
|
|
USART_NULL_PARAM_CHK(handle);
|
||
|
|
USART_NULL_PARAM_CHK(data);
|
||
|
|
|
||
|
|
if (num == 0) {
|
||
|
|
return ERR_USART(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
dw_usart_priv_t *usart_priv = handle;
|
||
|
|
uint8_t *source = NULL;
|
||
|
|
source = (uint8_t *)data;
|
||
|
|
|
||
|
|
usart_priv->tx_buf = (uint8_t *)data;
|
||
|
|
usart_priv->tx_total_num = num;
|
||
|
|
usart_priv->tx_cnt = 0;
|
||
|
|
usart_priv->tx_busy = 1;
|
||
|
|
|
||
|
|
dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base);
|
||
|
|
/* enable the interrupt*/
|
||
|
|
addr->IER |= IER_THRE_INT_ENABLE;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Abort Send data to UART transmitter
|
||
|
|
\param[in] handle usart handle to operate.
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_usart_abort_send(usart_handle_t handle)
|
||
|
|
{
|
||
|
|
USART_NULL_PARAM_CHK(handle);
|
||
|
|
dw_usart_priv_t *usart_priv = handle;
|
||
|
|
|
||
|
|
usart_priv->tx_cnt = usart_priv->tx_total_num;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Start receiving data from UART receiver.transmits the default value as specified by csi_usart_set_default_tx_value
|
||
|
|
\param[in] handle usart handle to operate.
|
||
|
|
\param[out] data Pointer to buffer for data to receive from UART receiver
|
||
|
|
\param[in] num Number of data items to receive
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_usart_receive(usart_handle_t handle, void *data, uint32_t num)
|
||
|
|
{
|
||
|
|
USART_NULL_PARAM_CHK(handle);
|
||
|
|
USART_NULL_PARAM_CHK(data);
|
||
|
|
|
||
|
|
uint8_t *dest = NULL;
|
||
|
|
dw_usart_priv_t *usart_priv = handle;
|
||
|
|
dest = (uint8_t *)data;
|
||
|
|
|
||
|
|
usart_priv->rx_buf = (uint8_t *)data; // Save receive buffer usart
|
||
|
|
usart_priv->rx_total_num = num; // Save number of data to be received
|
||
|
|
usart_priv->rx_cnt = 0;
|
||
|
|
usart_priv->rx_busy = 1;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief query data from UART receiver FIFO.
|
||
|
|
\param[in] handle usart handle to operate.
|
||
|
|
\param[out] data Pointer to buffer for data to receive from UART receiver
|
||
|
|
\param[in] num Number of data items to receive
|
||
|
|
\return receive fifo data num
|
||
|
|
*/
|
||
|
|
int32_t csi_usart_receive_query(usart_handle_t handle, void *data, uint32_t num)
|
||
|
|
{
|
||
|
|
USART_NULL_PARAM_CHK(handle);
|
||
|
|
USART_NULL_PARAM_CHK(data);
|
||
|
|
|
||
|
|
dw_usart_priv_t *usart_priv = handle;
|
||
|
|
dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base);
|
||
|
|
int32_t recv_num = 0;
|
||
|
|
|
||
|
|
while (addr->LSR & 0x1) {
|
||
|
|
*((uint8_t *)data++) = addr->RBR;
|
||
|
|
recv_num++;
|
||
|
|
|
||
|
|
if (recv_num >= num) {
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return recv_num;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Abort Receive data from UART receiver
|
||
|
|
\param[in] handle usart handle to operate.
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_usart_abort_receive(usart_handle_t handle)
|
||
|
|
{
|
||
|
|
USART_NULL_PARAM_CHK(handle);
|
||
|
|
dw_usart_priv_t *usart_priv = handle;
|
||
|
|
|
||
|
|
usart_priv->rx_cnt = usart_priv->rx_total_num;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Start sending/receiving data to/from UART transmitter/receiver.
|
||
|
|
\param[in] handle usart handle to operate.
|
||
|
|
\param[in] data_out Pointer to buffer with data to send to USART transmitter
|
||
|
|
\param[out] data_in Pointer to buffer for data to receive from USART receiver
|
||
|
|
\param[in] num Number of data items to transfer
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_usart_transfer(usart_handle_t handle, const void *data_out, void *data_in, uint32_t num)
|
||
|
|
{
|
||
|
|
USART_NULL_PARAM_CHK(handle);
|
||
|
|
return ERR_USART(EDRV_UNSUPPORTED);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief abort sending/receiving data to/from USART transmitter/receiver.
|
||
|
|
\param[in] handle usart handle to operate.
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_usart_abort_transfer(usart_handle_t handle)
|
||
|
|
{
|
||
|
|
USART_NULL_PARAM_CHK(handle);
|
||
|
|
return ERR_USART(EDRV_UNSUPPORTED);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Get USART status.
|
||
|
|
\param[in] handle usart handle to operate.
|
||
|
|
\return USART status \ref usart_status_t
|
||
|
|
*/
|
||
|
|
usart_status_t csi_usart_get_status(usart_handle_t handle)
|
||
|
|
{
|
||
|
|
usart_status_t usart_status;
|
||
|
|
dw_usart_priv_t *usart_priv = handle;
|
||
|
|
dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base);
|
||
|
|
uint32_t line_status_reg = addr->LSR;
|
||
|
|
|
||
|
|
usart_status.tx_busy = usart_priv->tx_busy;
|
||
|
|
usart_status.rx_busy = usart_priv->rx_busy;
|
||
|
|
|
||
|
|
if (line_status_reg & DW_LSR_BI) {
|
||
|
|
usart_status.rx_break = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (line_status_reg & DW_LSR_FE) {
|
||
|
|
usart_status.rx_framing_error = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (line_status_reg & DW_LSR_PE) {
|
||
|
|
usart_status.rx_parity_error = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
return usart_status;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief control the transmit.
|
||
|
|
\param[in] handle usart handle to operate.
|
||
|
|
\param[in] enable the transmitter.
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_usart_control_tx(usart_handle_t handle, bool enable)
|
||
|
|
{
|
||
|
|
USART_NULL_PARAM_CHK(handle);
|
||
|
|
return ERR_USART(EDRV_UNSUPPORTED);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief control the receive.
|
||
|
|
\param[in] handle usart handle to operate.
|
||
|
|
\param[in] enable the receive.
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_usart_control_rx(usart_handle_t handle, bool enable)
|
||
|
|
{
|
||
|
|
USART_NULL_PARAM_CHK(handle);
|
||
|
|
return ERR_USART(EDRV_UNSUPPORTED);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief control the break.
|
||
|
|
\param[in] handle usart handle to operate.
|
||
|
|
\param[in] enable the break.
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_usart_control_break(usart_handle_t handle, bool enable)
|
||
|
|
{
|
||
|
|
USART_NULL_PARAM_CHK(handle);
|
||
|
|
return ERR_USART(EDRV_UNSUPPORTED);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief flush receive/send data.
|
||
|
|
\param[in] handle usart handle to operate.
|
||
|
|
\param[in] type \ref usart_flush_type_e.
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_usart_flush(usart_handle_t handle, usart_flush_type_e type)
|
||
|
|
{
|
||
|
|
USART_NULL_PARAM_CHK(handle);
|
||
|
|
|
||
|
|
dw_usart_priv_t *usart_priv = handle;
|
||
|
|
dw_usart_reg_t *addr = (dw_usart_reg_t *)(usart_priv->base);
|
||
|
|
|
||
|
|
if (type == USART_FLUSH_WRITE) {
|
||
|
|
addr->FCR |= DW_FCR_XFIFOR;
|
||
|
|
} else if (type == USART_FLUSH_READ) {
|
||
|
|
addr->FCR |= DW_FCR_RFIFOR;
|
||
|
|
} else {
|
||
|
|
return ERR_USART(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|