2021-05-21 17:03:30 +08:00
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/01 Bernard The first version
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* 2018/12/27 Jesven Change irq enable/disable to cpu0
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*/
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#include "tick.h"
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#include <plic.h>
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#include "encoding.h"
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#include "riscv.h"
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#include "interrupt.h"
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#define CPU_NUM 2
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#define MAX_HANDLERS 128
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static struct rt_irq_desc irq_desc[MAX_HANDLERS];
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static rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
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{
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rt_kprintf("UN-handled interrupt %d occurred!!!\n", vector);
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return RT_NULL;
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}
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int rt_hw_clint_ipi_enable(void)
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{
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/* Set the Machine-Software bit in MIE */
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set_csr(mie, MIP_MSIP);
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return 0;
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}
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int rt_hw_clint_ipi_disable(void)
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{
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/* Clear the Machine-Software bit in MIE */
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clear_csr(mie, MIP_MSIP);
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return 0;
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}
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int rt_hw_plic_irq_enable(int irq_number)
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{
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plic_irq_enable(irq_number);
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return 0;
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}
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int rt_hw_plic_irq_disable(int irq_number)
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{
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plic_irq_disable(irq_number);
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return 0;
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}
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/**
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* This function will initialize hardware interrupt
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*/
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void rt_hw_interrupt_init(void)
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{
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int idx = 0;
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/* init exceptions table */
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for (idx = 0; idx < MAX_HANDLERS; idx++)
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{
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//rt_hw_interrupt_mask(idx);
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irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
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irq_desc[idx].param = RT_NULL;
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#ifdef RT_USING_INTERRUPT_INFO
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rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
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irq_desc[idx].counter = 0;
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#endif
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}
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}
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/**
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* This function will mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_mask(int vector)
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{
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rt_hw_plic_irq_disable(vector);
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}
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/**
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* This function will un-mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_umask(int vector)
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{
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plic_set_priority(vector, 1);
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plic_set_threshold(0);
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rt_hw_plic_irq_enable(vector);
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}
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/**
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* This function will install a interrupt service routine to a interrupt.
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* @param vector the interrupt number
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* @param new_handler the interrupt service routine to be installed
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* @param old_handler the old interrupt service routine
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*/
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rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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void *param, const char *name)
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{
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rt_isr_handler_t old_handler = RT_NULL;
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if(vector < MAX_HANDLERS)
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{
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old_handler = irq_desc[vector].handler;
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if (handler != RT_NULL)
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{
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irq_desc[vector].handler = (rt_isr_handler_t)handler;
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irq_desc[vector].param = param;
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#ifdef RT_USING_INTERRUPT_INFO
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rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
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irq_desc[vector].counter = 0;
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#endif
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}
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}
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return old_handler;
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}
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RT_WEAK
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void plic_irq_handle(int irq)
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{
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rt_kprintf("UN-handled interrupt %d occurred!!!\n", irq);
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return ;
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}
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void dump_regs(struct rt_hw_stack_frame *regs)
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{
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rt_kprintf("--------------Dump Registers-----------------\n");
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rt_kprintf("Function Registers:\n");
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rt_kprintf("\tra(x1) = 0x%p\tuser_sp = 0x%p\n",regs -> ra,regs -> user_sp_exc_stack);
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rt_kprintf("\tgp(x3) = 0x%p\ttp(x4) = 0x%p\n",regs -> gp,regs -> tp);
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rt_kprintf("Temporary Registers:\n");
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rt_kprintf("\tt0(x5) = 0x%p\tt1(x6) = 0x%p\n",regs -> t0,regs -> t1);
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rt_kprintf("\tt2(x7) = 0x%p\n",regs -> t2);
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rt_kprintf("\tt3(x28) = 0x%p\tt4(x29) = 0x%p\n",regs -> t3,regs -> t4);
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rt_kprintf("\tt5(x30) = 0x%p\tt6(x31) = 0x%p\n",regs -> t5,regs -> t6);
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rt_kprintf("Saved Registers:\n");
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rt_kprintf("\ts0/fp(x8) = 0x%p\ts1(x9) = 0x%p\n",regs -> s0_fp,regs -> s1);
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rt_kprintf("\ts2(x18) = 0x%p\ts3(x19) = 0x%p\n",regs -> s2,regs -> s3);
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rt_kprintf("\ts4(x20) = 0x%p\ts5(x21) = 0x%p\n",regs -> s4,regs -> s5);
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rt_kprintf("\ts6(x22) = 0x%p\ts7(x23) = 0x%p\n",regs -> s6,regs -> s7);
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rt_kprintf("\ts8(x24) = 0x%p\ts9(x25) = 0x%p\n",regs -> s8,regs -> s9);
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rt_kprintf("\ts10(x26) = 0x%p\ts11(x27) = 0x%p\n",regs -> s10,regs -> s11);
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rt_kprintf("Function Arguments Registers:\n");
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rt_kprintf("\ta0(x10) = 0x%p\ta1(x11) = 0x%p\n",regs -> a0,regs -> a1);
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rt_kprintf("\ta2(x12) = 0x%p\ta3(x13) = 0x%p\n",regs -> a2,regs -> a3);
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rt_kprintf("\ta4(x14) = 0x%p\ta5(x15) = 0x%p\n",regs -> a4,regs -> a5);
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rt_kprintf("\ta6(x16) = 0x%p\ta7(x17) = 0x%p\n",regs -> a6,regs -> a7);
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rt_kprintf("xstatus = 0x%p\n",regs -> xstatus);
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rt_kprintf("\t%s\n",(regs -> xstatus & SSTATUS_SIE) ? "Supervisor Interrupt Enabled" : "Supervisor Interrupt Disabled");
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rt_kprintf("\t%s\n",(regs -> xstatus & SSTATUS_SPIE) ? "Last Time Supervisor Interrupt Enabled" : "Last Time Supervisor Interrupt Disabled");
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rt_kprintf("\t%s\n",(regs -> xstatus & SSTATUS_SPP) ? "Last Privilege is Supervisor Mode" : "Last Privilege is User Mode");
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rt_kprintf("\t%s\n",(regs -> xstatus & SSTATUS_PUM) ? "Permit to Access User Page" : "Not Permit to Access User Page");
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rt_kprintf("\t%s\n",(regs -> xstatus & (1 << 19)) ? "Permit to Read Executable-only Page" : "Not Permit to Read Executable-only Page");
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rt_size_t satp_v = read_csr(satp);
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rt_kprintf("satp = 0x%p\n",satp_v);
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const char *mode_str = "Unknown Address Translation/Protection Mode";
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2021-05-21 18:39:41 +08:00
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2021-05-21 17:03:30 +08:00
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switch(__MASKVALUE(satp_v >> 60,__MASK(4)))
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{
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case 0:
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mode_str = "No Address Translation/Protection Mode";
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break;
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case 8:
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mode_str = "Page-based 39-bit Virtual Addressing Mode";
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break;
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case 9:
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mode_str = "Page-based 48-bit Virtual Addressing Mode";
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break;
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}
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rt_kprintf("\tMode = %s\n",mode_str);
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rt_kprintf("-----------------Dump OK---------------------\n");
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}
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void handle_trap(rt_size_t xcause,rt_size_t xtval,rt_size_t xepc,struct rt_hw_stack_frame *sp)
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{
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int cause = (xcause & 0xFFFFFFFF);
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int plic_irq = 0;
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if (xcause & (1UL << 63))
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{
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switch (cause)
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{
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case IRQ_M_SOFT:
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{
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2021-05-21 18:39:41 +08:00
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2021-05-21 17:03:30 +08:00
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}
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break;
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case IRQ_M_TIMER:
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tick_isr();
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break;
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case IRQ_S_TIMER:
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tick_isr();
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break;
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case IRQ_S_EXT:
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plic_irq = plic_claim();
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plic_complete(plic_irq);
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irq_desc[plic_irq].handler(plic_irq, irq_desc[plic_irq].param);
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break;
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case IRQ_M_EXT:
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plic_irq = plic_claim();
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plic_complete(plic_irq);
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irq_desc[plic_irq].handler(plic_irq, irq_desc[plic_irq].param);
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break;
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}
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}
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else
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{
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rt_thread_t tid;
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2021-08-29 04:48:08 +08:00
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#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
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2021-05-21 17:03:30 +08:00
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extern long list_thread();
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2021-08-26 07:10:01 +08:00
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#endif
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2021-05-21 17:03:30 +08:00
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rt_hw_interrupt_disable();
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rt_kprintf("xcause = %08x,xtval = %08x,xepc = %08x\n", xcause, xtval, xepc);
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tid = rt_thread_self();
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rt_kprintf("\nException:\n");
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switch (cause)
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{
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case CAUSE_MISALIGNED_FETCH:
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rt_kprintf("Instruction address misaligned");
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break;
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case CAUSE_FAULT_FETCH:
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rt_kprintf("Instruction access fault");
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break;
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case CAUSE_ILLEGAL_INSTRUCTION:
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rt_kprintf("Illegal instruction");
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break;
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case CAUSE_BREAKPOINT:
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rt_kprintf("Breakpoint");
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break;
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case CAUSE_MISALIGNED_LOAD:
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rt_kprintf("Load address misaligned");
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break;
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case CAUSE_FAULT_LOAD:
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rt_kprintf("Load access fault");
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break;
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case CAUSE_MISALIGNED_STORE:
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rt_kprintf("Store address misaligned");
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break;
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case CAUSE_FAULT_STORE:
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rt_kprintf("Store access fault");
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break;
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case CAUSE_USER_ECALL:
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rt_kprintf("Environment call from U-mode");
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break;
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case CAUSE_SUPERVISOR_ECALL:
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rt_kprintf("Environment call from S-mode");
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break;
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case CAUSE_HYPERVISOR_ECALL:
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rt_kprintf("Environment call from H-mode");
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break;
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case CAUSE_MACHINE_ECALL:
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rt_kprintf("Environment call from M-mode");
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break;
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default:
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rt_kprintf("Uknown exception : %08lX", cause);
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break;
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}
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rt_kprintf("\n");
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dump_regs(sp);
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rt_kprintf("exception pc => 0x%08x\n", xepc);
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rt_kprintf("current thread: %.*s\n", RT_NAME_MAX, tid->name);
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2021-08-29 04:48:08 +08:00
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#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
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2021-05-21 17:03:30 +08:00
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list_thread();
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#endif
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while(1);
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}
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rt_hw_interrupt_enable(0);
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}
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